kkd.map.rpt

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源码 开发软件 Quartus II

; Type of Retiming Performed During Resynthesis                      ; Full               ;                    ;
; Resynthesis Optimization Effort                                    ; Normal             ;                    ;
; Physical Synthesis Level for Resynthesis                           ; Normal             ;                    ;
; Use Generated Physical Constraints File                            ; On                 ;                    ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Safe State Machine                                                 ; Off                ; Off                ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Ignore Verilog initial constructs                                  ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- MAX II                                   ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM Block Balancing                                           ; On                 ; On                 ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                  ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                              ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                              ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------+
; kkd.bdf                          ; yes             ; User Block Diagram/Schematic File  ; E:/for_extent/test_cpld_1/test_cpld/kkd.bdf               ;
; com_to_lpt.v                     ; yes             ; User Verilog HDL File              ; E:/for_extent/test_cpld_1/test_cpld/com_to_lpt.v          ;
; D_trigger.v                      ; yes             ; User Verilog HDL File              ; E:/for_extent/test_cpld_1/test_cpld/D_trigger.v           ;
; fw_delay.v                       ; yes             ; User Verilog HDL File              ; E:/for_extent/test_cpld_1/test_cpld/fw_delay.v            ;
; JK_trigger.v                     ; yes             ; User Verilog HDL File              ; E:/for_extent/test_cpld_1/test_cpld/JK_trigger.v          ;
; modu4.bdf                        ; yes             ; User Block Diagram/Schematic File  ; E:/for_extent/test_cpld_1/test_cpld/modu4.bdf             ;
; modu5.v                          ; yes             ; User Verilog HDL File              ; E:/for_extent/test_cpld_1/test_cpld/modu5.v               ;
; mux2.v                           ; yes             ; User Verilog HDL File              ; E:/for_extent/test_cpld_1/test_cpld/mux2.v                ;
; qei_filter.bdf                   ; yes             ; User Block Diagram/Schematic File  ; E:/for_extent/test_cpld_1/test_cpld/qei_filter.bdf        ;
; qei_top.bdf                      ; yes             ; User Block Diagram/Schematic File  ; E:/for_extent/test_cpld_1/test_cpld/qei_top.bdf           ;
; sdi_buf.v                        ; yes             ; User Verilog HDL File              ; E:/for_extent/test_cpld_1/test_cpld/sdi_buf.v             ;
; sent_buf.v                       ; yes             ; User Verilog HDL File              ; E:/for_extent/test_cpld_1/test_cpld/sent_buf.v            ;
; shift_clk.v                      ; yes             ; User Verilog HDL File              ; E:/for_extent/test_cpld_1/test_cpld/shift_clk.v           ;
; xx4x.bdf                         ; yes             ; User Block Diagram/Schematic File  ; E:/for_extent/test_cpld_1/test_cpld/xx4x.bdf              ;
; xx164x.bdf                       ; yes             ; User Block Diagram/Schematic File  ; E:/for_extent/test_cpld_1/test_cpld/xx164x.bdf            ;