dram_tmp.v

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源码 开发软件 Quartus II

module dram_tmp(rst,clk,ad_over,ad_lz,ad_zx,ad_hx,ad_zx_out,ad_lz_out,ad_hx_out,code1_in,code1_out,code2_in,code2_out,sdo_sign,ad_cycle_end,position_in,position_out);
input        rst;
input        clk;
input        sdo_sign;
input        ad_cycle_end;
input        ad_over;
input[23:0]  ad_lz;
input[23:0]  ad_zx;
input[23:0]  ad_hx;
input[31:0]  position_in;
input[31:0]  code1_in;
input[31:0]  code2_in;
output[31:0] position_out;
output[24:0] ad_lz_out;
output[23:0] ad_zx_out;
output[23:0] ad_hx_out;
output[31:0] code1_out;
output[31:0] code2_out;
reg[31:0]    position_out;
reg[24:0]    ad_lz_out;
reg[23:0]    ad_zx_out;
reg[23:0]    ad_hx_out;
reg[31:0]    code1_out;
reg[31:0]    code2_out;
reg          inn1;
reg          inn2;
reg          imm1;
reg          imm2;
reg          imm3;

always @(posedge clk or negedge rst)
begin
if(!rst)
   begin
   imm1<=1'b0;
   imm2<=1'b0;
   end
else
   begin
   imm1<=sdo_sign;
   imm2<=imm1;
   end
end

always @(posedge clk or negedge rst)
begin
if(!rst)
imm3<=1'b0;
else if(imm1==1'b0)
       begin
       if(imm2==1'b1)
         imm3<=1'b1;
       else
         imm3<=1'b0;
       end
else
imm3<=1'b0;
end

always @(posedge clk or negedge rst)
begin
if(!rst)
begin
position_out<=32'b0;
code1_out<=32'b0;
code2_out<=32'b0;
end
else if(imm3==1'b1)
       begin
       if(ad_cycle_end==1'b0)
       begin
       code1_out<=code1_in;
       code2_out<=code2_in;
       position_out<=position_in;
       end
       else
       begin
       position_out<=position_out;
       code1_out<=code1_out;
       code2_out<=code2_out;
       end
       end
else
begin
position_out<=position_out;
code1_out<=code1_out;
code2_out<=code2_out;
end
end

//always @(posedge clk or negedge rst)
//begin
//if(!rst)
//position_out<=33'b0;
//else if(imm3==1'b1)
//       begin
//       if(ad_cycle_end==1'b0)
//          begin
//          position_out[31:0]<=position_in;
//          if(position_out[32]==1'b0)
//          position_out[32]<=1'b1;
//          else
//          position_out[32]<=1'b0;
//          end
//       else
//          begin
//          position_out<=position_out;
//          end
//       end
//else
//position_out<=position_out;
//end


always @(posedge clk or negedge rst)
begin
if(!rst)
   begin
   inn1<=1'b0;
   inn2<=1'b0;
   end
else
   begin
   inn1<=ad_over;
   inn2<=inn1;
   end
end

always @(posedge clk or negedge rst)
begin
if(!rst)
begin
ad_lz_out<=25'b0;
ad_zx_out<=24'b0;
ad_hx_out<=24'b0;
end
else if(inn1==1'b1)
     begin
     if(inn2==1'b0)
        begin
        ad_lz_out[23:0]<=ad_lz[23:0];
        ad_zx_out[23:0]<=ad_zx[23:0];  
		ad_hx_out[23:0]<=ad_hx[23:0];       
        if(ad_lz_out[24]==1'b0) 
        ad_lz_out[24]<=1'b1;
        else
        ad_lz_out[24]<=1'b0;
        end
     else
        begin
		ad_hx_out<=ad_hx_out;
        ad_zx_out<=ad_zx_out;        
        ad_lz_out<=ad_lz_out;
        end
     end
else
   begin
   ad_hx_out<=ad_hx_out;
   ad_zx_out<=ad_zx_out;        
   ad_lz_out<=ad_lz_out;
   end
end

endmodule