kkd.fit.smsg

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集源码 开发软件 Quartus II

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Wed Oct 15 16:06:21 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off kkd -c kkd
Info: Selected device EPM1270T144C5 for design "kkd"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM1270T144I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLK" to use Global clock in PIN 89
Info: Automatically promoted some destinations of signal "fenpin1000:inst55|clk_divi" to use Global clock
    Info: Destination "shift_clk:inst13|ttp" may be non-global or may not use global clock
    Info: Destination "shift_clk:inst20|ttp" may be non-global or may not use global clock
    Info: Destination "shift_clk:inst54|ttp" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "shift_clk:inst13|clk_shift" to use Global clock
    Info: Destination "SCLK0" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "shift_clk:inst20|clk_shift" to use Global clock
    Info: Destination "SCLK1" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:05
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:10
Info: Estimated most critical path is register to register delay of 4.324 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y7; Fanout = 1; REG Node = 'sdi_buf:inst6|all_cycle'
    Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LAB_X6_Y7; Fanout = 96; COMB Node = 'dram_tmp:inst46|position_out[31]~2863'
    Info: 3: + IC(2.486 ns) + CELL(1.243 ns) = 4.324 ns; Loc. = LAB_X8_Y8; Fanout = 1; REG Node = 'dram_tmp:inst46|code1_out[22]'
    Info: Total cell delay = 1.838 ns ( 42.51 % )
    Info: Total interconnect delay = 2.486 ns ( 57.49 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 17% of the available device resources. Peak interconnect usage is 23%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:03
Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Allocated 160 megabytes of memory during processing
    Info: Processing ended: Wed Oct 15 16:06:44 2008
    Info: Elapsed time: 00:00:23