dds.map.qmsg

来自「FPGA，vhdl语言的学习资料」· QMSG 代码 · 共 43 行 · 第 1/5 页

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sAltrPropagate SBF:Souti\|sAltrPropagate:u0 " "Info: Elaborating entity \"sAltrPropagate\" for hierarchy \"SBF:Souti\|sAltrPropagate:u0\"" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "u0" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 932 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SBF SBF:AltBusi " "Info: Elaborating entity \"SBF\" for hierarchy \"SBF:AltBusi\"" {  } { { "DDS.vhd" "AltBusi" { Text "D:/my_eda3/DDS/DDS.vhd" 103 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sAltrPropagate SBF:AltBusi\|sAltrPropagate:u0 " "Info: Elaborating entity \"sAltrPropagate\" for hierarchy \"SBF:AltBusi\|sAltrPropagate:u0\"" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "u0" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 932 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SDelay SDelay:Delayi " "Info: Elaborating entity \"SDelay\" for hierarchy \"SDelay:Delayi\"" {  } { { "DDS.vhd" "Delayi" { Text "D:/my_eda3/DDS/DDS.vhd" 117 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sAltrPropagate SDelay:Delayi\|sAltrPropagate:u0 " "Info: Elaborating entity \"sAltrPropagate\" for hierarchy \"SDelay:Delayi\|sAltrPropagate:u0\"" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "u0" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1297 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AltiMult AltiMult:Producti " "Info: Elaborating entity \"AltiMult\" for hierarchy \"AltiMult:Producti\"" {  } { { "DDS.vhd" "Producti" { Text "D:/my_eda3/DDS/DDS.vhd" 130 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SAdderSub SAdderSub:ParallelAdderSubtractori " "Info: Elaborating entity \"SAdderSub\" for hierarchy \"SAdderSub:ParallelAdderSubtractori\"" {  } { { "DDS.vhd" "ParallelAdderSubtractori" { Text "D:/my_eda3/DDS/DDS.vhd" 151 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/70/quartus/libraries/megafunctions/LPM_ADD_SUB.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/LPM_ADD_SUB.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "LPM_ADD_SUB.tdf" "" { Text "e:/altera/70/quartus/libraries/megafunctions/LPM_ADD_SUB.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ADD_SUB SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0 " "Info: Elaborating entity \"LPM_ADD_SUB\" for hierarchy \"SAdderSub:ParallelAdderSubtractori\|LPM_ADD_SUB:\\pip:genaa:U0\"" {  } { { "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" "\\pip:genaa:U0" { Text "e:/altera/70/DSPBuilder/Altlib/DSPBUILDER.VHD" 1876 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}