dds_top.fit.smsg

FPGA，vhdl语言的学习资料

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Sat May 05 19:28:41 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dds_top -c dds_top
Info: Automatically selected device EP1S10F484C5 for design dds_top
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 200 of 200 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1S20F484C5 is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
    Info: Pin ~DATA0~ is reserved at location L8
Warning: No exact pin location assignment(s) for 62 pins of 62 total pins
    Info: Pin Sout[0] not assigned to an exact location on the device
    Info: Pin Sout[1] not assigned to an exact location on the device
    Info: Pin Sout[2] not assigned to an exact location on the device
    Info: Pin Sout[3] not assigned to an exact location on the device
    Info: Pin Sout[4] not assigned to an exact location on the device
    Info: Pin Sout[5] not assigned to an exact location on the device
    Info: Pin Sout[6] not assigned to an exact location on the device
    Info: Pin Sout[7] not assigned to an exact location on the device
    Info: Pin Sout[8] not assigned to an exact location on the device
    Info: Pin Sout[9] not assigned to an exact location on the device
    Info: Pin clock not assigned to an exact location on the device
    Info: Pin sclrp not assigned to an exact location on the device
    Info: Pin Aword[0] not assigned to an exact location on the device
    Info: Pin Aword[1] not assigned to an exact location on the device
    Info: Pin Aword[2] not assigned to an exact location on the device
    Info: Pin Aword[3] not assigned to an exact location on the device
    Info: Pin Aword[4] not assigned to an exact location on the device
    Info: Pin Aword[5] not assigned to an exact location on the device
    Info: Pin Aword[6] not assigned to an exact location on the device
    Info: Pin Aword[7] not assigned to an exact location on the device
    Info: Pin Aword[8] not assigned to an exact location on the device
    Info: Pin Aword[9] not assigned to an exact location on the device
    Info: Pin Pword[0] not assigned to an exact location on the device
    Info: Pin Pword[1] not assigned to an exact location on the device
    Info: Pin Pword[2] not assigned to an exact location on the device
    Info: Pin Pword[3] not assigned to an exact location on the device
    Info: Pin Pword[4] not assigned to an exact location on the device
    Info: Pin Pword[5] not assigned to an exact location on the device
    Info: Pin Pword[6] not assigned to an exact location on the device
    Info: Pin Pword[7] not assigned to an exact location on the device
    Info: Pin Fword[22] not assigned to an exact location on the device
    Info: Pin Fword[23] not assigned to an exact location on the device
    Info: Pin Fword[24] not assigned to an exact location on the device
    Info: Pin Fword[25] not assigned to an exact location on the device
    Info: Pin Fword[26] not assigned to an exact location on the device
    Info: Pin Fword[27] not assigned to an exact location on the device
    Info: Pin Fword[21] not assigned to an exact location on the device
    Info: Pin Fword[28] not assigned to an exact location on the device
    Info: Pin Fword[29] not assigned to an exact location on the device
    Info: Pin Fword[30] not assigned to an exact location on the device
    Info: Pin Fword[31] not assigned to an exact location on the device
    Info: Pin Fword[20] not assigned to an exact location on the device
    Info: Pin Fword[19] not assigned to an exact location on the device
    Info: Pin Fword[18] not assigned to an exact location on the device
    Info: Pin Fword[17] not assigned to an exact location on the device
    Info: Pin Fword[16] not assigned to an exact location on the device
    Info: Pin Fword[15] not assigned to an exact location on the device
    Info: Pin Fword[14] not assigned to an exact location on the device
    Info: Pin Fword[13] not assigned to an exact location on the device
    Info: Pin Fword[12] not assigned to an exact location on the device
    Info: Pin Fword[11] not assigned to an exact location on the device
    Info: Pin Fword[10] not assigned to an exact location on the device
    Info: Pin Fword[9] not assigned to an exact location on the device
    Info: Pin Fword[8] not assigned to an exact location on the device
    Info: Pin Fword[7] not assigned to an exact location on the device
    Info: Pin Fword[6] not assigned to an exact location on the device
    Info: Pin Fword[5] not assigned to an exact location on the device
    Info: Pin Fword[4] not assigned to an exact location on the device
    Info: Pin Fword[3] not assigned to an exact location on the device
    Info: Pin Fword[2] not assigned to an exact location on the device
    Info: Pin Fword[1] not assigned to an exact location on the device
    Info: Pin Fword[0] not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clock" to use Global clock in PIN M20
Info: Automatically promoted some destinations of signal "sclrp" to use Global clock in PIN M21
    Info: Destination "DDS:DDSi|AltiMult:Producti|resdtb[10]" may be non-global or may not use global clock
    Info: Destination "DDS:DDSi|AltiMult:Producti|resdtb[11]" may be non-global or may not use global clock
    Info: Destination "DDS:DDSi|AltiMult:Producti|resdtb[12]" may be non-global or may not use global clock
    Info: Destination "DDS:DDSi|AltiMult:Producti|resdtb[13]" may be non-global or may not use global clock
    Info: Destination "DDS:DDSi|AltiMult:Producti|resdtb[14]" may be non-global or may not use global clock
    Info: Destination "DDS:DDSi|AltiMult:Producti|resdtb[15]" may be non-global or may not use global clock
    Info: Destination "DDS:DDSi|AltiMult:Producti|resdtb[16]" may be non-global or may not use global clock
    Info: Destination "DDS:DDSi|AltiMult:Producti|resdtb[17]" may be non-global or may not use global clock
    Info: Destination "DDS:DDSi|AltiMult:Producti|resdtb[18]" may be non-global or may not use global clock
    Info: Destination "DDS:DDSi|AltiMult:Producti|resdtb[19]" may be non-global or may not use global clock
    Info: Limited to 10 non-global destinations
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 60 (unused VREF, 3.30 VCCIO, 50 input, 10 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  27 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  30 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  51 pins available
        Info: I/O bank number 5 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  29 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  52 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  51 pins available
        Info: I/O bank number 9 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 10 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
        Info: I/O bank number 11 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  6 pins available
        Info: I/O bank number 12 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  0 pins available
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is memory to register delay of 11.271 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X37_Y18; Fanout = 1; MEM Node = 'DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a0~porta_address_reg9'
    Info: 2: + IC(0.000 ns) + CELL(3.069 ns) = 3.069 ns; Loc. = M4K_X37_Y18; Fanout = 1; MEM Node = 'DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|q_a[0]'
    Info: 3: + IC(0.777 ns) + CELL(0.280 ns) = 4.126 ns; Loc. = LAB_X39_Y17; Fanout = 22; COMB Node = 'DDS:DDSi|AltiMult:Producti|dataaint~212'
    Info: 4: + IC(1.344 ns) + CELL(3.451 ns) = 8.921 ns; Loc. = DSPMULT_X42_Y15_N0; Fanout = 10; COMB Node = 'DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|mac_mult2~DATAOUT21'
    Info: 5: + IC(0.000 ns) + CELL(0.878 ns) = 9.799 ns; Loc. = DSPOUT_X43_Y9_N0; Fanout = 1; COMB Node = 'DDS:DDSi|AltiMult:Producti|lpm_mult:Mult0|mult_6h01:auto_generated|result[13]'
    Info: 6: + IC(0.933 ns) + CELL(0.539 ns) = 11.271 ns; Loc. = LAB_X41_Y12; Fanout = 1; REG Node = 'DDS:DDSi|AltiMult:Producti|resdtb[13]'
    Info: Total cell delay = 8.217 ns ( 72.90 % )
    Info: Total interconnect delay = 3.054 ns ( 27.10 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%
    Info: The peak interconnect region extends from location X32_Y10 to location X42_Y20
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 206 megabytes of memory during processing
    Info: Processing ended: Sat May 05 19:29:11 2007
    Info: Elapsed time: 00:00:30