dds_top.tan.rpt

FPGA，vhdl语言的学习资料

+------------------------------+----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S10F484C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; fmax Requirement                                      ; 20 ns              ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------+---------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                         ; To                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------+---------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 8.518 ns                                ; 87.09 MHz ( period = 11.482 ns )                    ; DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9 ; DDS:DDSi|AltiMult:Producti|resdtb[12] ; clock      ; clock    ; 20.000 ns                   ; 19.595 ns                 ; 11.077 ns               ;
; 8.518 ns                                ; 87.09 MHz ( period = 11.482 ns )                    ; DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg8 ; DDS:DDSi|AltiMult:Producti|resdtb[12] ; clock      ; clock    ; 20.000 ns                   ; 19.595 ns                 ; 11.077 ns               ;
; 8.518 ns                                ; 87.09 MHz ( period = 11.482 ns )                    ; DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg7 ; DDS:DDSi|AltiMult:Producti|resdtb[12] ; clock      ; clock    ; 20.000 ns                   ; 19.595 ns                 ; 11.077 ns               ;
; 8.518 ns                                ; 87.09 MHz ( period = 11.482 ns )                    ; DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg6 ; DDS:DDSi|AltiMult:Producti|resdtb[12] ; clock      ; clock    ; 20.000 ns                   ; 19.595 ns                 ; 11.077 ns               ;
; 8.518 ns                                ; 87.09 MHz ( period = 11.482 ns )                    ; DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg5 ; DDS:DDSi|AltiMult:Producti|resdtb[12] ; clock      ; clock    ; 20.000 ns                   ; 19.595 ns                 ; 11.077 ns               ;
; 8.518 ns                                ; 87.09 MHz ( period = 11.482 ns )                    ; DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg4 ; DDS:DDSi|AltiMult:Producti|resdtb[12] ; clock      ; clock    ; 20.000 ns                   ; 19.595 ns                 ; 11.077 ns               ;
; 8.518 ns                                ; 87.09 MHz ( period = 11.482 ns )                    ; DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg3 ; DDS:DDSi|AltiMult:Producti|resdtb[12] ; clock      ; clock    ; 20.000 ns                   ; 19.595 ns                 ; 11.077 ns               ;
; 8.518 ns                                ; 87.09 MHz ( period = 11.482 ns )                    ; DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg2 ; DDS:DDSi|AltiMult:Producti|resdtb[12] ; clock      ; clock    ; 20.000 ns                   ; 19.595 ns                 ; 11.077 ns               ;