dds_top.tan.summary

FPGA，vhdl语言的学习资料

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.306 ns
From           : Pword[4]
To             : DDS:DDSi|SAdderSub:ParallelAdderSubtractor1i|lpm_add_sub:\pip:genaa:U0|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3]
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.342 ns
From           : DDS:DDSi|AltiMult:Producti|resdtb[10]
To             : Sout[0]
From Clock     : clock
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.155 ns
From           : sclrp
To             : DDS:DDSi|SDelay:Delayi|result[9]
From Clock     : --
To Clock       : clock
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : 8.518 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 87.09 MHz ( period = 11.482 ns )
From           : DDS:DDSi|altsyncram:Mux0_rtl_0|altsyncram_bju:auto_generated|ram_block1a1~porta_address_reg9
To             : DDS:DDSi|AltiMult:Producti|resdtb[12]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Clock Hold: 'clock'
Slack          : 0.886 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10]
To             : DDS:DDSi|SAdderSub:ParallelAdderSubtractori|lpm_add_sub:\pip:genaa:U0|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[10]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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