tm1375.h

s1d13716的源码 windiws ce 或8位单片机

/************************************************************************
 *									*
 *	Copyright (C) SEIKO EPSON CORP. 1999				*
 *									*
 *	File name: tm1375.h						*
 *	  This is lcd controller driver header file.			*
 *									*
 *	Revision history						*
 *		2001.06.22	Mike.Chen	Start.			*
 *		1999.04.22	T.Mineshima	Define modify.		*
 *									*
 ************************************************************************/
#define 	LCD_ADDRESS	0x2000000
#define		LCDRAM_ADDR		0x00d40
#define 	SED1375_REGISTER	0x203ffc0
/* Address definition */
//#define		SED1375_RECO_ADDR		0x203ffc0//0x201ffe0		// Address for revision code 
#define		SED1375_MOD0_ADDR		0x203ffc3//0x201ffe1		// Address for mode register 0
#define		SED1375_MOD1_ADDR		0x203ffc4//0x201ffe2		// Address for mode register 1
#define		SED1375_MOD2_ADDR		0x203ffc7//0x201ffe3		// Address for mode register 2

#define		SED1375_HPANSI_ADDR		0x203ffc8//0x201ffe4		// Address for horizontal panel size register
#define		SED1375_VPANSIL_ADDR		0x203ffcb//0x201ffe5		// Address for vertical panel size register(lsb)
#define		SED1375_VPANSIH_ADDR		0x203ffcc//0x201ffe6		// Address for vertical panel size register(msb)
#define		SED1375_FPLINESP_ADDR		0x203ffcf//0x201ffe7		// Address for fpline start position

#define		SED1375_HNONDISP_ADDR		0x203ffd0//0x201ffe8		// Address for horizontal non-display period
#define		SED1375_FPFRAMESP_ADDR		0x203ffd3//0x201ffe9		// Address for fpframe start sosition
#define		SED1375_VNONDISP_ADDR		0x203ffd4//0x201ffea		// Address for vertical non-display period
#define		SED1375_MODRATE_ADDR		0x203ffd7//0x201ffeb		// Address for mod rate register

#define		SED1375_SCR1SADDL_ADDR		0x203ffd8//0x201ffec		// Address for screen 1 start address register(lsb)
#define		SED1375_SCR1SADDM_ADDR		0x203ffdb//0x201ffed		// Address for screen 1 start address register(msb)
#define		SED1375_SCR2SADDL_ADDR		0x203ffdc//0x201ffee		// Address for screen 2 start address register(lsb)
#define		SED1375_SCR2SADDM_ADDR		0x203ffdf//0x201ffef		// Address for screen 2 start address register(msb)

#define		SED1375_SCRSADDOF_ADDR		0x203ffe0//0x201fff0		// Address for screen start address overflow register
#define		SED1375_MEMADDOFF_ADDR		0x203ffe3//0x201fff1		// Address for memory address offset register
#define		SED1375_SCR1VSL_ADDR		0x203ffe4//0x201fff2		// Address for screen 1 vertical size register(lsb)
#define		SED1375_SCR1VSM_ADDR		0x203ffe7//0x201fff3		// Address for screen 1 vertical size register(msb)

#define		SED1375_LUTABADDR_ADDR		0x203ffeb//0x201fff5		// Address for look-up table address register
#define		SED1375_LUTABDAT_ADDR		0x203ffef//0x201fff7		// Address for look-up table data register

#define		SED1375_GPIOCONFIGC_ADDR	0x203fff0//0x201fff8		// Address for GPIO configuration control register
#define		SED1375_GPIOSTACON_ADDR		0x203fff3//0x201fff9		// Address for GPIO status/control register
#define		SED1375_SCRPAD_ADDR		0x203fff4//0x201fffa		// Address for scratch pad register
#define		SED1375_VIEWMOD_ADDR		0x203fff7//0x201fffb		// Address for swiveview mode register

#define		SED1375_LBCR_ADDR		0x203fff8//0x201fffc		// Address for line byte counter register for swiveview mode

/* Bit field definition */
//REG01h
#define		S75_SELMOD_TFT		0x80		// TFT/MD-DTFD is selected
#define		S75_SELMOD_STN		0x00		// STN(PASSIVE) is selected

#define		S75_SELPAN_DUAL		0x40		// dual panel lcd driver is selected
#define		S75_SELPAN_SIN		0x00		// single panel lcd driver is selected

#define		S75_SELCOL		0x20		// color lcd driver
#define		S75_SELMONO		0x00		// monochrome lcd dirver

#define		S75_SELLPOL_LOW		0x00		// fpline porarity active low
#define		S75_SELLPOL_HIGH	0x10		// fpline porarity active high

#define		S75_SELFPOL_LOW		0x00		// fpframe porarity active low
#define		S75_SELFPOL_HIGH	0x08		// fpframe porarity active high

#define		S75_FPSHIFT_MASK	0x04		// FPSHIFT is masked during non-display periods

#define		S75_DATAWIDTH_00	0x00		
#define		S75_DATAWIDTH_01	0x01
#define		S75_DATAWIDTH_10	0x10
#define		S75_DATAWIDTH_11	0x11


//REG02h
#define		S75_CLKSEL_HIGH		0x00		// operating clk=clki
#define		S75_CLKSEL_LOW		0x10		// operating clk=clki/2

#define		S75_BLANK_ON		0x08		// display image is blanked
#define		S75_BLANK_OFF		0x00		// display image is enable

#define		S75_FRMREP_ENA		0x04		// frame repeat enable
#define		S75_FRMREP_DIS		0x00		// frame repeat disable

#define		S75_HWIVT_ENA		0x02		// hardware video invert is enable via fpdat11
#define		S75_HWIVT_DIS		0x00	

#define		S75_SWIVT_ENA		0x01		// software video invert is selected
	

//reg03h
#define		S75_LCDPWR_ON		0x00		// LCD power is controlled by sequencing logic
#define		S75_LCDPWR_OFF		0x08		//LCD power is forced to off

#define		S75_HWPSAVE_ENA		0x04		//GPIO0 is used as hardware power save input io
#define		S75_HWPSAVE_DIS 	0x00		//GPIO0 operates normally

#define		S75_SWPSAVE_ON		0x00		//software power save on
#define		S75_SWPSAVE_OFF 	0x03		//software power save off

//reg18h
#define		S75_GPIO0_FUN		0x01		//set GPIO0 as output
#define		S75_GPIO1_FUN		0x02		//set GPIO1 as output
#define		S75_GPIO2_FUN		0x04		//set GPIO2 as output
#define		S75_GPIO3_FUN		0x08		//set GPIO3 as output
#define		S75_GPIO4_FUN		0x10		//set GPIO4 as output

//reg1Bh
#define		S75_VIEWMOD_ENA		0x80	        //swivemode is selected
#define		S75_LANDMOD_ENA		0x00	        //landscape mode is enable

#define		S75_VIEWMOD_ALT 	0x40		//alternate swivemode is selected
#define		S75_VIEWMOD_DFT 	0x00		//alternate swivemode is selected