vga.tan.qmsg

基于FPGA的VGA接口显示程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "VGA.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { { 128 24 192 144 "clk" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "reset " "Info: Assuming node \"reset\" is an undefined clock" {  } { { "VGA.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { { 144 24 192 160 "reset" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "VGAsignal:inst\|clk_25 " "Info: Detected ripple clock \"VGAsignal:inst\|clk_25\" as buffer" {  } { { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 25 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGAsignal:inst\|clk_25" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "VGAsignal:inst\|VGA_HS " "Info: Detected ripple clock \"VGAsignal:inst\|VGA_HS\" as buffer" {  } { { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 20 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGAsignal:inst\|VGA_HS" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register VGAsignal:inst\|LL\[5\] register VGAsignal:inst\|LL\[1\] 233.59 MHz 4.281 ns Internal " "Info: Clock \"clk\" has Internal fmax of 233.59 MHz between source register \"VGAsignal:inst\|LL\[5\]\" and destination register \"VGAsignal:inst\|LL\[1\]\" (period= 4.281 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.017 ns + Longest register register " "Info: + Longest register to register delay is 4.017 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsignal:inst\|LL\[5\] 1 REG LCFF_X21_Y13_N21 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y13_N21; Fanout = 7; REG Node = 'VGAsignal:inst\|LL\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsignal:inst|LL[5] } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.111 ns) + CELL(0.370 ns) 1.481 ns VGAsignal:inst\|LessThan10~183 2 COMB LCCOMB_X20_Y13_N4 5 " "Info: 2: + IC(1.111 ns) + CELL(0.370 ns) = 1.481 ns; Loc. = LCCOMB_X20_Y13_N4; Fanout = 5; COMB Node = 'VGAsignal:inst\|LessThan10~183'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.481 ns" { VGAsignal:inst|LL[5] VGAsignal:inst|LessThan10~183 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 116 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.370 ns) 2.247 ns VGAsignal:inst\|Equal5~108 3 COMB LCCOMB_X20_Y13_N2 2 " "Info: 3: + IC(0.396 ns) + CELL(0.370 ns) = 2.247 ns; Loc. = LCCOMB_X20_Y13_N2; Fanout = 2; COMB Node = 'VGAsignal:inst\|Equal5~108'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.766 ns" { VGAsignal:inst|LessThan10~183 VGAsignal:inst|Equal5~108 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 94 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.206 ns) 2.823 ns VGAsignal:inst\|LessThan1~137 4 COMB LCCOMB_X20_Y13_N14 11 " "Info: 4: + IC(0.370 ns) + CELL(0.206 ns) = 2.823 ns; Loc. = LCCOMB_X20_Y13_N14; Fanout = 11; COMB Node = 'VGAsignal:inst\|LessThan1~137'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.576 ns" { VGAsignal:inst|Equal5~108 VGAsignal:inst|LessThan1~137 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.660 ns) 4.017 ns VGAsignal:inst\|LL\[1\] 5 REG LCFF_X21_Y13_N13 7 " "Info: 5: + IC(0.534 ns) + CELL(0.660 ns) = 4.017 ns; Loc. = LCFF_X21_Y13_N13; Fanout = 7; REG Node = 'VGAsignal:inst\|LL\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.194 ns" { VGAsignal:inst|LessThan1~137 VGAsignal:inst|LL[1] } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.606 ns ( 39.98 % ) " "Info: Total cell delay = 1.606 ns ( 39.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.411 ns ( 60.02 % ) " "Info: Total interconnect delay = 2.411 ns ( 60.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.017 ns" { VGAsignal:inst|LL[5] VGAsignal:inst|LessThan10~183 VGAsignal:inst|Equal5~108 VGAsignal:inst|LessThan1~137 VGAsignal:inst|LL[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.017 ns" { VGAsignal:inst|LL[5] {} VGAsignal:inst|LessThan10~183 {} VGAsignal:inst|Equal5~108 {} VGAsignal:inst|LessThan1~137 {} VGAsignal:inst|LL[1] {} } { 0.000ns 1.111ns 0.396ns 0.370ns 0.534ns } { 0.000ns 0.370ns 0.370ns 0.206ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.462 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.462 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { { 128 24 192 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.632 ns VGAsignal:inst\|clk_25 2 REG LCFF_X1_Y6_N3 3 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.632 ns; Loc. = LCFF_X1_Y6_N3; Fanout = 3; REG Node = 'VGAsignal:inst\|clk_25'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk VGAsignal:inst|clk_25 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.154 ns) + CELL(0.970 ns) 5.756 ns VGAsignal:inst\|VGA_HS 3 REG LCFF_X25_Y7_N31 4 " "Info: 3: + IC(2.154 ns) + CELL(0.970 ns) = 5.756 ns; Loc. = LCFF_X25_Y7_N31; Fanout = 4; REG Node = 'VGAsignal:inst\|VGA_HS'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.124 ns" { VGAsignal:inst|clk_25 VGAsignal:inst|VGA_HS } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.179 ns) + CELL(0.000 ns) 6.935 ns VGAsignal:inst\|VGA_HS~clkctrl 4 COMB CLKCTRL_G6 12 " "Info: 4: + IC(1.179 ns) + CELL(0.000 ns) = 6.935 ns; Loc. = CLKCTRL_G6; Fanout = 12; COMB Node = 'VGAsignal:inst\|VGA_HS~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.179 ns" { VGAsignal:inst|VGA_HS VGAsignal:inst|VGA_HS~clkctrl } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.666 ns) 8.462 ns VGAsignal:inst\|LL\[1\] 5 REG LCFF_X21_Y13_N13 7 " "Info: 5: + IC(0.861 ns) + CELL(0.666 ns) = 8.462 ns; Loc. = LCFF_X21_Y13_N13; Fanout = 7; REG Node = 'VGAsignal:inst\|LL\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { VGAsignal:inst|VGA_HS~clkctrl VGAsignal:inst|LL[1] } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 44.27 % ) " "Info: Total cell delay = 3.746 ns ( 44.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.716 ns ( 55.73 % ) " "Info: Total interconnect delay = 4.716 ns ( 55.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.462 ns" { clk VGAsignal:inst|clk_25 VGAsignal:inst|VGA_HS VGAsignal:inst|VGA_HS~clkctrl VGAsignal:inst|LL[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.462 ns" { clk {} clk~combout {} VGAsignal:inst|clk_25 {} VGAsignal:inst|VGA_HS {} VGAsignal:inst|VGA_HS~clkctrl {} VGAsignal:inst|LL[1] {} } { 0.000ns 0.000ns 0.522ns 2.154ns 1.179ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.462 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.462 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGA.bdf" { { 128 24 192 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.632 ns VGAsignal:inst\|clk_25 2 REG LCFF_X1_Y6_N3 3 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.632 ns; Loc. = LCFF_X1_Y6_N3; Fanout = 3; REG Node = 'VGAsignal:inst\|clk_25'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk VGAsignal:inst|clk_25 } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.154 ns) + CELL(0.970 ns) 5.756 ns VGAsignal:inst\|VGA_HS 3 REG LCFF_X25_Y7_N31 4 " "Info: 3: + IC(2.154 ns) + CELL(0.970 ns) = 5.756 ns; Loc. = LCFF_X25_Y7_N31; Fanout = 4; REG Node = 'VGAsignal:inst\|VGA_HS'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.124 ns" { VGAsignal:inst|clk_25 VGAsignal:inst|VGA_HS } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.179 ns) + CELL(0.000 ns) 6.935 ns VGAsignal:inst\|VGA_HS~clkctrl 4 COMB CLKCTRL_G6 12 " "Info: 4: + IC(1.179 ns) + CELL(0.000 ns) = 6.935 ns; Loc. = CLKCTRL_G6; Fanout = 12; COMB Node = 'VGAsignal:inst\|VGA_HS~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.179 ns" { VGAsignal:inst|VGA_HS VGAsignal:inst|VGA_HS~clkctrl } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.666 ns) 8.462 ns VGAsignal:inst\|LL\[5\] 5 REG LCFF_X21_Y13_N21 7 " "Info: 5: + IC(0.861 ns) + CELL(0.666 ns) = 8.462 ns; Loc. = LCFF_X21_Y13_N21; Fanout = 7; REG Node = 'VGAsignal:inst\|LL\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { VGAsignal:inst|VGA_HS~clkctrl VGAsignal:inst|LL[5] } "NODE_NAME" } } { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 44.27 % ) " "Info: Total cell delay = 3.746 ns ( 44.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.716 ns ( 55.73 % ) " "Info: Total interconnect delay = 4.716 ns ( 55.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.462 ns" { clk VGAsignal:inst|clk_25 VGAsignal:inst|VGA_HS VGAsignal:inst|VGA_HS~clkctrl VGAsignal:inst|LL[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.462 ns" { clk {} clk~combout {} VGAsignal:inst|clk_25 {} VGAsignal:inst|VGA_HS {} VGAsignal:inst|VGA_HS~clkctrl {} VGAsignal:inst|LL[5] {} } { 0.000ns 0.000ns 0.522ns 2.154ns 1.179ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.462 ns" { clk VGAsignal:inst|clk_25 VGAsignal:inst|VGA_HS VGAsignal:inst|VGA_HS~clkctrl VGAsignal:inst|LL[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.462 ns" { clk {} clk~combout {} VGAsignal:inst|clk_25 {} VGAsignal:inst|VGA_HS {} VGAsignal:inst|VGA_HS~clkctrl {} VGAsignal:inst|LL[1] {} } { 0.000ns 0.000ns 0.522ns 2.154ns 1.179ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.462 ns" { clk VGAsignal:inst|clk_25 VGAsignal:inst|VGA_HS VGAsignal:inst|VGA_HS~clkctrl VGAsignal:inst|LL[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.462 ns" { clk {} clk~combout {} VGAsignal:inst|clk_25 {} VGAsignal:inst|VGA_HS {} VGAsignal:inst|VGA_HS~clkctrl {} VGAsignal:inst|LL[5] {} } { 0.000ns 0.000ns 0.522ns 2.154ns 1.179ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 98 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "VGAsignal.v" "" { Text "D:/FPGA开发板/开发板资料/EP2C5_EP2C8-V5资料/例子工程/EP2C5-V5/VGA_v/VGAsignal.v" 98 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.017 ns" { VGAsignal:inst|LL[5] VGAsignal:inst|LessThan10~183 VGAsignal:inst|Equal5~108 VGAsignal:inst|LessThan1~137 VGAsignal:inst|LL[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.017 ns" { VGAsignal:inst|LL[5] {} VGAsignal:inst|LessThan10~183 {} VGAsignal:inst|Equal5~108 {} VGAsignal:inst|LessThan1~137 {} VGAsignal:inst|LL[1] {} } { 0.000ns 1.111ns 0.396ns 0.370ns 0.534ns } { 0.000ns 0.370ns 0.370ns 0.206ns 0.660ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.462 ns" { clk VGAsignal:inst|clk_25 VGAsignal:inst|VGA_HS VGAsignal:inst|VGA_HS~clkctrl VGAsignal:inst|LL[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.462 ns" { clk {} clk~combout {} VGAsignal:inst|clk_25 {} VGAsignal:inst|VGA_HS {} VGAsignal:inst|VGA_HS~clkctrl {} VGAsignal:inst|LL[1] {} } { 0.000ns 0.000ns 0.522ns 2.154ns 1.179ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.462 ns" { clk VGAsignal:inst|clk_25 VGAsignal:inst|VGA_HS VGAsignal:inst|VGA_HS~clkctrl VGAsignal:inst|LL[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.462 ns" { clk {} clk~combout {} VGAsignal:inst|clk_25 {} VGAsignal:inst|VGA_HS {} VGAsignal:inst|VGA_HS~clkctrl {} VGAsignal:inst|LL[5] {} } { 0.000ns 0.000ns 0.522ns 2.154ns 1.179ns 0.861ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}