vga.hier_info

基于FPGA的VGA接口显示程序

|VGA
VGA_HS <= VGAsignal:inst.VGA_HS
clk => VGAsignal:inst.CLK
reset => VGAsignal:inst.MD
VGA_VS <= VGAsignal:inst.VGA_VS
VGA_R <= VGAsignal:inst.R
VGA_G <= VGAsignal:inst.G
VGA_B <= VGAsignal:inst.B


|VGA|VGAsignal:inst
CLK => clk_25.CLK
MD => MMD[1].CLK
MD => MMD[0].CLK
MD => GRB~6.IN0
MD => GRB~3.IN0
MD => GRB~0.IN0
MD => VGA_VS~reg0.PRESET
MD => LL[0].ACLR
MD => LL[1].ACLR
MD => LL[2].ACLR
MD => LL[3].ACLR
MD => LL[4].ACLR
MD => LL[5].ACLR
MD => LL[6].ACLR
MD => LL[7].ACLR
MD => LL[8].ACLR
MD => LL[9].ACLR
MD => LL[10].ACLR
MD => CC[10].ACLR
MD => CC[9].ACLR
MD => CC[8].ACLR
MD => CC[7].ACLR
MD => CC[6].ACLR
MD => CC[5].ACLR
MD => CC[4].ACLR
MD => CC[3].ACLR
MD => CC[2].ACLR
MD => CC[1].ACLR
MD => CC[0].ACLR
MD => VGA_HS~reg0.PRESET
VGA_HS <= VGA_HS~reg0.DB_MAX_OUTPUT_PORT_TYPE
VGA_VS <= VGA_VS~reg0.DB_MAX_OUTPUT_PORT_TYPE
R <= GRB~5.DB_MAX_OUTPUT_PORT_TYPE
G <= GRB~8.DB_MAX_OUTPUT_PORT_TYPE
B <= GRB~2.DB_MAX_OUTPUT_PORT_TYPE