dff8.vhd

来自「通过VHDL语言进行数字信号处理的FIR操作」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY dff8 IS 
PORT( clk :   IN  STD_LOGIC;
 	  clear : IN  STD_LOGIC;
	  Din :     IN  STD_LOGIC_VECTOR(7 DOWNTO 0); 
	  Dout :     OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); 
END dff8; 

ARCHITECTURE a OF dff8 IS 
BEGIN 
  PROCESS(clk,clear) 
    BEGIN 
	  IF clear='1' THEN
		 Dout<="00000000";
	  ELSIF clear='0' THEN
	    IF(clk'EVENT AND clk='1') THEN
		 Dout <= Din;
	    END IF; 
	  END IF; 
  END PROCESS; 
END a;