fir.tan.summary

来自「通过VHDL语言进行数字信号处理的FIR操作」· SUMMARY 代码 · 共 57 行

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.899 ns
From           : Din[2]
To             : add889:inst18|Dout[6]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.850 ns
From           : add888:inst44|Dout[5]
To             : Dout[5]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.088 ns
From           : Din[4]
To             : dff8:inst2|Dout[4]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 120.08 MHz ( period = 8.328 ns )
From           : dff89:inst34|Dout[0]
To             : mult242:inst40|Dout[15]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------