fir.tan.qmsg

通过VHDL语言进行数字信号处理的FIR操作

{ "Info" "ITDB_FULL_TCO_RESULT" "clk Dout\[5\] add888:inst44\|Dout\[5\] 5.850 ns register " "Info: tco from clock \"clk\" to destination pin \"Dout\[5\]\" through register \"add888:inst44\|Dout\[5\]\" is 5.850 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.110 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 435; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "" { clk } "NODE_NAME" } "" } } { "fir.bdf" "" { Schematic "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.547 ns) 2.110 ns add888:inst44\|Dout\[5\] 2 REG LC_X15_Y5_N5 1 " "Info: 2: + IC(0.433 ns) + CELL(0.547 ns) = 2.110 ns; Loc. = LC_X15_Y5_N5; Fanout = 1; REG Node = 'add888:inst44\|Dout\[5\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.980 ns" { clk add888:inst44|Dout[5] } "NODE_NAME" } "" } } { "add888.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/add888.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.48 % " "Info: Total cell delay = 1.677 ns ( 79.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.433 ns 20.52 % " "Info: Total interconnect delay = 0.433 ns ( 20.52 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "2.110 ns" { clk add888:inst44|Dout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 add888:inst44|Dout[5] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "add888.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/add888.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.567 ns + Longest register pin " "Info: + Longest register to pin delay is 3.567 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add888:inst44\|Dout\[5\] 1 REG LC_X15_Y5_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y5_N5; Fanout = 1; REG Node = 'add888:inst44\|Dout\[5\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "" { add888:inst44|Dout[5] } "NODE_NAME" } "" } } { "add888.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/add888.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.945 ns) + CELL(1.622 ns) 3.567 ns Dout\[5\] 2 PIN PIN_86 0 " "Info: 2: + IC(1.945 ns) + CELL(1.622 ns) = 3.567 ns; Loc. = PIN_86; Fanout = 0; PIN Node = 'Dout\[5\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "3.567 ns" { add888:inst44|Dout[5] Dout[5] } "NODE_NAME" } "" } } { "fir.bdf" "" { Schematic "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/fir.bdf" { { 1024 1512 1688 1040 "Dout\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 45.47 % " "Info: Total cell delay = 1.622 ns ( 45.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.945 ns 54.53 % " "Info: Total interconnect delay = 1.945 ns ( 54.53 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "3.567 ns" { add888:inst44|Dout[5] Dout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.567 ns" { add888:inst44|Dout[5] Dout[5] } { 0.000ns 1.945ns } { 0.000ns 1.622ns } } }  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "2.110 ns" { clk add888:inst44|Dout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.110 ns" { clk clk~out0 add888:inst44|Dout[5] } { 0.000ns 0.000ns 0.433ns } { 0.000ns 1.130ns 0.547ns } } } { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "3.567 ns" { add888:inst44|Dout[5] Dout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.567 ns" { add888:inst44|Dout[5] Dout[5] } { 0.000ns 1.945ns } { 0.000ns 1.622ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "dff8:inst2\|Dout\[4\] Din\[4\] clk -3.088 ns register " "Info: th for register \"dff8:inst2\|Dout\[4\]\" (data pin = \"Din\[4\]\", clock pin = \"clk\") is -3.088 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.128 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 435; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "" { clk } "NODE_NAME" } "" } } { "fir.bdf" "" { Schematic "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns dff8:inst2\|Dout\[4\] 2 REG LC_X12_Y12_N1 3 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X12_Y12_N1; Fanout = 3; REG Node = 'dff8:inst2\|Dout\[4\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.998 ns" { clk dff8:inst2|Dout[4] } "NODE_NAME" } "" } } { "dff8.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/dff8.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "2.128 ns" { clk dff8:inst2|Dout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 dff8:inst2|Dout[4] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "dff8.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/dff8.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.228 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.228 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns Din\[4\] 1 PIN PIN_89 3 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_89; Fanout = 3; PIN Node = 'Din\[4\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "" { Din[4] } "NODE_NAME" } "" } } { "fir.bdf" "" { Schematic "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/fir.bdf" { { 120 -64 104 136 "Din\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.855 ns) + CELL(0.238 ns) 5.228 ns dff8:inst2\|Dout\[4\] 2 REG LC_X12_Y12_N1 3 " "Info: 2: + IC(3.855 ns) + CELL(0.238 ns) = 5.228 ns; Loc. = LC_X12_Y12_N1; Fanout = 3; REG Node = 'dff8:inst2\|Dout\[4\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "4.093 ns" { Din[4] dff8:inst2|Dout[4] } "NODE_NAME" } "" } } { "dff8.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/dff8.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.373 ns 26.26 % " "Info: Total cell delay = 1.373 ns ( 26.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.855 ns 73.74 % " "Info: Total interconnect delay = 3.855 ns ( 73.74 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "5.228 ns" { Din[4] dff8:inst2|Dout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.228 ns" { Din[4] Din[4]~out0 dff8:inst2|Dout[4] } { 0.000ns 0.000ns 3.855ns } { 0.000ns 1.135ns 0.238ns } } }  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "2.128 ns" { clk dff8:inst2|Dout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 dff8:inst2|Dout[4] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "5.228 ns" { Din[4] dff8:inst2|Dout[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.228 ns" { Din[4] Din[4]~out0 dff8:inst2|Dout[4] } { 0.000ns 0.000ns 3.855ns } { 0.000ns 1.135ns 0.238ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 05 21:22:06 2008 " "Info: Processing ended: Wed Mar 05 21:22:06 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}