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📄 fir.tan.qmsg

📁 通过VHDL语言进行数字信号处理的FIR操作
💻 QMSG
📖 第 1 页 / 共 4 页
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "fir.bdf" "" { Schematic "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register dff89:inst34\|Dout\[0\] register mult242:inst40\|Dout\[14\] 120.08 MHz 8.328 ns Internal " "Info: Clock \"clk\" has Internal fmax of 120.08 MHz between source register \"dff89:inst34\|Dout\[0\]\" and destination register \"mult242:inst40\|Dout\[14\]\" (period= 8.328 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.126 ns + Longest register register " "Info: + Longest register to register delay is 8.126 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dff89:inst34\|Dout\[0\] 1 REG LC_X8_Y13_N3 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y13_N3; Fanout = 21; REG Node = 'dff89:inst34\|Dout\[0\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "" { dff89:inst34|Dout[0] } "NODE_NAME" } "" } } { "dff89.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/dff89.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.616 ns) + CELL(0.443 ns) 1.059 ns mult242:inst40\|add~2106COUT1_2185 2 COMB LC_X9_Y13_N0 2 " "Info: 2: + IC(0.616 ns) + CELL(0.443 ns) = 1.059 ns; Loc. = LC_X9_Y13_N0; Fanout = 2; COMB Node = 'mult242:inst40\|add~2106COUT1_2185'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "1.059 ns" { dff89:inst34|Dout[0] mult242:inst40|add~2106COUT1_2185 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.121 ns mult242:inst40\|add~2075COUT1_2187 3 COMB LC_X9_Y13_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.121 ns; Loc. = LC_X9_Y13_N1; Fanout = 2; COMB Node = 'mult242:inst40\|add~2075COUT1_2187'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.062 ns" { mult242:inst40|add~2106COUT1_2185 mult242:inst40|add~2075COUT1_2187 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.183 ns mult242:inst40\|add~2044COUT1_2189 4 COMB LC_X9_Y13_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.183 ns; Loc. = LC_X9_Y13_N2; Fanout = 2; COMB Node = 'mult242:inst40\|add~2044COUT1_2189'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.062 ns" { mult242:inst40|add~2075COUT1_2187 mult242:inst40|add~2044COUT1_2189 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 1.651 ns mult242:inst40\|add~2032 5 COMB LC_X9_Y13_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.468 ns) = 1.651 ns; Loc. = LC_X9_Y13_N3; Fanout = 2; COMB Node = 'mult242:inst40\|add~2032'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.468 ns" { mult242:inst40|add~2044COUT1_2189 mult242:inst40|add~2032 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.546 ns) + CELL(0.645 ns) 2.842 ns mult242:inst40\|add~1943 6 COMB LC_X10_Y13_N9 6 " "Info: 6: + IC(0.546 ns) + CELL(0.645 ns) = 2.842 ns; Loc. = LC_X10_Y13_N9; Fanout = 6; COMB Node = 'mult242:inst40\|add~1943'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "1.191 ns" { mult242:inst40|add~2032 mult242:inst40|add~1943 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.523 ns) 3.365 ns mult242:inst40\|add~1931 7 COMB LC_X10_Y12_N0 3 " "Info: 7: + IC(0.000 ns) + CELL(0.523 ns) = 3.365 ns; Loc. = LC_X10_Y12_N0; Fanout = 3; COMB Node = 'mult242:inst40\|add~1931'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.523 ns" { mult242:inst40|add~1943 mult242:inst40|add~1931 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.161 ns) + CELL(0.333 ns) 4.859 ns mult242:inst40\|add~1850COUT1_2225 8 COMB LC_X9_Y9_N0 2 " "Info: 8: + IC(1.161 ns) + CELL(0.333 ns) = 4.859 ns; Loc. = LC_X9_Y9_N0; Fanout = 2; COMB Node = 'mult242:inst40\|add~1850COUT1_2225'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "1.494 ns" { mult242:inst40|add~1931 mult242:inst40|add~1850COUT1_2225 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 4.921 ns mult242:inst40\|add~1839COUT1_2227 9 COMB LC_X9_Y9_N1 2 " "Info: 9: + IC(0.000 ns) + CELL(0.062 ns) = 4.921 ns; Loc. = LC_X9_Y9_N1; Fanout = 2; COMB Node = 'mult242:inst40\|add~1839COUT1_2227'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.062 ns" { mult242:inst40|add~1850COUT1_2225 mult242:inst40|add~1839COUT1_2227 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 5.389 ns mult242:inst40\|add~1826 10 COMB LC_X9_Y9_N2 1 " "Info: 10: + IC(0.000 ns) + CELL(0.468 ns) = 5.389 ns; Loc. = LC_X9_Y9_N2; Fanout = 1; COMB Node = 'mult242:inst40\|add~1826'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.468 ns" { mult242:inst40|add~1839COUT1_2227 mult242:inst40|add~1826 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.532 ns) + CELL(0.454 ns) 6.375 ns mult242:inst40\|add~1836 11 COMB LC_X8_Y9_N6 3 " "Info: 11: + IC(0.532 ns) + CELL(0.454 ns) = 6.375 ns; Loc. = LC_X8_Y9_N6; Fanout = 3; COMB Node = 'mult242:inst40\|add~1836'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.986 ns" { mult242:inst40|add~1826 mult242:inst40|add~1836 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.434 ns) 7.343 ns mult242:inst40\|Dout\[12\]~117 12 COMB LC_X7_Y9_N3 2 " "Info: 12: + IC(0.534 ns) + CELL(0.434 ns) = 7.343 ns; Loc. = LC_X7_Y9_N3; Fanout = 2; COMB Node = 'mult242:inst40\|Dout\[12\]~117'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.968 ns" { mult242:inst40|add~1836 mult242:inst40|Dout[12]~117 } "NODE_NAME" } "" } } { "mult242.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/mult242.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.137 ns) 7.480 ns mult242:inst40\|Dout\[13\]~113 13 COMB LC_X7_Y9_N4 2 " "Info: 13: + IC(0.000 ns) + CELL(0.137 ns) = 7.480 ns; Loc. = LC_X7_Y9_N4; Fanout = 2; COMB Node = 'mult242:inst40\|Dout\[13\]~113'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.137 ns" { mult242:inst40|Dout[12]~117 mult242:inst40|Dout[13]~113 } "NODE_NAME" } "" } } { "mult242.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/mult242.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.646 ns) 8.126 ns mult242:inst40\|Dout\[14\] 14 REG LC_X7_Y9_N5 1 " "Info: 14: + IC(0.000 ns) + CELL(0.646 ns) = 8.126 ns; Loc. = LC_X7_Y9_N5; Fanout = 1; REG Node = 'mult242:inst40\|Dout\[14\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.646 ns" { mult242:inst40|Dout[13]~113 mult242:inst40|Dout[14] } "NODE_NAME" } "" } } { "mult242.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/mult242.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.737 ns 58.29 % " "Info: Total cell delay = 4.737 ns ( 58.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.389 ns 41.71 % " "Info: Total interconnect delay = 3.389 ns ( 41.71 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "8.126 ns" { dff89:inst34|Dout[0] mult242:inst40|add~2106COUT1_2185 mult242:inst40|add~2075COUT1_2187 mult242:inst40|add~2044COUT1_2189 mult242:inst40|add~2032 mult242:inst40|add~1943 mult242:inst40|add~1931 mult242:inst40|add~1850COUT1_2225 mult242:inst40|add~1839COUT1_2227 mult242:inst40|add~1826 mult242:inst40|add~1836 mult242:inst40|Dout[12]~117 mult242:inst40|Dout[13]~113 mult242:inst40|Dout[14] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.126 ns" { dff89:inst34|Dout[0] mult242:inst40|add~2106COUT1_2185 mult242:inst40|add~2075COUT1_2187 mult242:inst40|add~2044COUT1_2189 mult242:inst40|add~2032 mult242:inst40|add~1943 mult242:inst40|add~1931 mult242:inst40|add~1850COUT1_2225 mult242:inst40|add~1839COUT1_2227 mult242:inst40|add~1826 mult242:inst40|add~1836 mult242:inst40|Dout[12]~117 mult242:inst40|Dout[13]~113 mult242:inst40|Dout[14] } { 0.000ns 0.616ns 0.000ns 0.000ns 0.000ns 0.546ns 0.000ns 1.161ns 0.000ns 0.000ns 0.532ns 0.534ns 0.000ns 0.000ns } { 0.000ns 0.443ns 0.062ns 0.062ns 0.468ns 0.645ns 0.523ns 0.333ns 0.062ns 0.468ns 0.454ns 0.434ns 0.137ns 0.646ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.128 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 435; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "" { clk } "NODE_NAME" } "" } } { "fir.bdf" "" { Schematic "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns mult242:inst40\|Dout\[14\] 2 REG LC_X7_Y9_N5 1 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X7_Y9_N5; Fanout = 1; REG Node = 'mult242:inst40\|Dout\[14\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.998 ns" { clk mult242:inst40|Dout[14] } "NODE_NAME" } "" } } { "mult242.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/mult242.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "2.128 ns" { clk mult242:inst40|Dout[14] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 mult242:inst40|Dout[14] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.128 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 435; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "" { clk } "NODE_NAME" } "" } } { "fir.bdf" "" { Schematic "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns dff89:inst34\|Dout\[0\] 2 REG LC_X8_Y13_N3 21 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X8_Y13_N3; Fanout = 21; REG Node = 'dff89:inst34\|Dout\[0\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.998 ns" { clk dff89:inst34|Dout[0] } "NODE_NAME" } "" } } { "dff89.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/dff89.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "2.128 ns" { clk dff89:inst34|Dout[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 dff89:inst34|Dout[0] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "2.128 ns" { clk mult242:inst40|Dout[14] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 mult242:inst40|Dout[14] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "2.128 ns" { clk dff89:inst34|Dout[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 dff89:inst34|Dout[0] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "dff89.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/dff89.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "mult242.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/mult242.vhd" 8 -1 0 } }  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "8.126 ns" { dff89:inst34|Dout[0] mult242:inst40|add~2106COUT1_2185 mult242:inst40|add~2075COUT1_2187 mult242:inst40|add~2044COUT1_2189 mult242:inst40|add~2032 mult242:inst40|add~1943 mult242:inst40|add~1931 mult242:inst40|add~1850COUT1_2225 mult242:inst40|add~1839COUT1_2227 mult242:inst40|add~1826 mult242:inst40|add~1836 mult242:inst40|Dout[12]~117 mult242:inst40|Dout[13]~113 mult242:inst40|Dout[14] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.126 ns" { dff89:inst34|Dout[0] mult242:inst40|add~2106COUT1_2185 mult242:inst40|add~2075COUT1_2187 mult242:inst40|add~2044COUT1_2189 mult242:inst40|add~2032 mult242:inst40|add~1943 mult242:inst40|add~1931 mult242:inst40|add~1850COUT1_2225 mult242:inst40|add~1839COUT1_2227 mult242:inst40|add~1826 mult242:inst40|add~1836 mult242:inst40|Dout[12]~117 mult242:inst40|Dout[13]~113 mult242:inst40|Dout[14] } { 0.000ns 0.616ns 0.000ns 0.000ns 0.000ns 0.546ns 0.000ns 1.161ns 0.000ns 0.000ns 0.532ns 0.534ns 0.000ns 0.000ns } { 0.000ns 0.443ns 0.062ns 0.062ns 0.468ns 0.645ns 0.523ns 0.333ns 0.062ns 0.468ns 0.454ns 0.434ns 0.137ns 0.646ns } } } { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "2.128 ns" { clk mult242:inst40|Dout[14] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 mult242:inst40|Dout[14] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "2.128 ns" { clk dff89:inst34|Dout[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 dff89:inst34|Dout[0] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "add889:inst18\|Dout\[5\] Din\[2\] clk 4.899 ns register " "Info: tsu for register \"add889:inst18\|Dout\[5\]\" (data pin = \"Din\[2\]\", clock pin = \"clk\") is 4.899 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.998 ns + Longest pin register " "Info: + Longest pin to register delay is 6.998 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns Din\[2\] 1 PIN PIN_98 4 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_98; Fanout = 4; PIN Node = 'Din\[2\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "" { Din[2] } "NODE_NAME" } "" } } { "fir.bdf" "" { Schematic "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/fir.bdf" { { 120 -64 104 136 "Din\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.694 ns) + CELL(0.326 ns) 6.155 ns add889:inst18\|Dout\[2\]~88 2 COMB LC_X11_Y10_N2 2 " "Info: 2: + IC(4.694 ns) + CELL(0.326 ns) = 6.155 ns; Loc. = LC_X11_Y10_N2; Fanout = 2; COMB Node = 'add889:inst18\|Dout\[2\]~88'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "5.020 ns" { Din[2] add889:inst18|Dout[2]~88 } "NODE_NAME" } "" } } { "add889.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/add889.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 6.215 ns add889:inst18\|Dout\[3\]~84 3 COMB LC_X11_Y10_N3 2 " "Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 6.215 ns; Loc. = LC_X11_Y10_N3; Fanout = 2; COMB Node = 'add889:inst18\|Dout\[3\]~84'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.060 ns" { add889:inst18|Dout[2]~88 add889:inst18|Dout[3]~84 } "NODE_NAME" } "" } } { "add889.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/add889.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.137 ns) 6.352 ns add889:inst18\|Dout\[4\]~80 4 COMB LC_X11_Y10_N4 4 " "Info: 4: + IC(0.000 ns) + CELL(0.137 ns) = 6.352 ns; Loc. = LC_X11_Y10_N4; Fanout = 4; COMB Node = 'add889:inst18\|Dout\[4\]~80'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.137 ns" { add889:inst18|Dout[3]~84 add889:inst18|Dout[4]~80 } "NODE_NAME" } "" } } { "add889.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/add889.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.646 ns) 6.998 ns add889:inst18\|Dout\[5\] 5 REG LC_X11_Y10_N5 5 " "Info: 5: + IC(0.000 ns) + CELL(0.646 ns) = 6.998 ns; Loc. = LC_X11_Y10_N5; Fanout = 5; REG Node = 'add889:inst18\|Dout\[5\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.646 ns" { add889:inst18|Dout[4]~80 add889:inst18|Dout[5] } "NODE_NAME" } "" } } { "add889.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/add889.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.304 ns 32.92 % " "Info: Total cell delay = 2.304 ns ( 32.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.694 ns 67.08 % " "Info: Total interconnect delay = 4.694 ns ( 67.08 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "6.998 ns" { Din[2] add889:inst18|Dout[2]~88 add889:inst18|Dout[3]~84 add889:inst18|Dout[4]~80 add889:inst18|Dout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.998 ns" { Din[2] Din[2]~out0 add889:inst18|Dout[2]~88 add889:inst18|Dout[3]~84 add889:inst18|Dout[4]~80 add889:inst18|Dout[5] } { 0.000ns 0.000ns 4.694ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.135ns 0.326ns 0.060ns 0.137ns 0.646ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "add889.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/add889.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.128 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 435 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 435; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "" { clk } "NODE_NAME" } "" } } { "fir.bdf" "" { Schematic "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/fir.bdf" { { 88 -64 104 104 "clk" "" } { 80 376 416 96 "clk" "" } { 80 640 672 96 "clk" "" } { 264 104 128 280 "clk" "" } { 264 336 376 280 "clk" "" } { 264 592 632 280 "clk" "" } { 264 840 872 280 "clk" "" } { 264 1072 1120 280 "clk" "" } { 264 1336 1360 280 "clk" "" } { 264 1568 1600 280 "clk" "" } { 264 1840 1864 280 "clk" "" } { 80 864 904 96 "clk" "" } { 80 1104 1152 96 "clk" "" } { 80 1352 1392 96 "clk" "" } { 80 1592 1632 96 "clk" "" } { 80 1848 1904 96 "clk" "" } { 400 2056 2104 416 "clk" "" } { 400 1784 1848 416 "clk" "" } { 400 1544 1592 416 "clk" "" } { 400 1304 1352 416 "clk" "" } { 400 1048 1104 416 "clk" "" } { 400 816 872 416 "clk" "" } { 400 568 624 416 "clk" "" } { 400 320 376 416 "clk" "" } { 80 104 176 96 "clk" "" } { 496 80 96 528 "clk" "" } { 500 368 384 528 "clk" "" } { 500 856 872 528 "clk" "" } { 496 1352 1368 528 "clk" "" } { 500 1848 1864 528 "clk" "" } { 500 544 560 528 "clk" "" } { 496 1088 1104 528 "clk" "" } { 496 1568 1584 528 "clk" "" } { 752 120 144 768 "clk" "" } { 752 624 664 768 "clk" "" } { 752 1128 1152 768 "clk" "" } { 752 1600 1632 768 "clk" "" } { 944 432 480 960 "clk" "" } { 1096 432 480 1112 "clk" "" } { 1008 744 808 1024 "clk" "" } { 1016 1192 1288 1032 "clk" "" } { 740 1968 1984 768 "clk" "" } { 748 2112 2128 776 "clk" "" } { 500 2128 2144 528 "clk" "" } { 960 2112 2128 1056 "clk" "" } { 264 2096 2118 280 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns add889:inst18\|Dout\[5\] 2 REG LC_X11_Y10_N5 5 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X11_Y10_N5; Fanout = 5; REG Node = 'add889:inst18\|Dout\[5\]'" {  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "0.998 ns" { clk add889:inst18|Dout[5] } "NODE_NAME" } "" } } { "add889.vhd" "" { Text "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/add889.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "2.128 ns" { clk add889:inst18|Dout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 add889:inst18|Dout[5] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "6.998 ns" { Din[2] add889:inst18|Dout[2]~88 add889:inst18|Dout[3]~84 add889:inst18|Dout[4]~80 add889:inst18|Dout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.998 ns" { Din[2] Din[2]~out0 add889:inst18|Dout[2]~88 add889:inst18|Dout[3]~84 add889:inst18|Dout[4]~80 add889:inst18|Dout[5] } { 0.000ns 0.000ns 4.694ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.135ns 0.326ns 0.060ns 0.137ns 0.646ns } } } { "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" "" { Report "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir_cmp.qrpt" Compiler "fir" "UNKNOWN" "V1" "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/db/fir.quartus_db" { Floorplan "C:/Documents and Settings/zjczhang/桌面/fir滤波器/firOK/" "" "2.128 ns" { clk add889:inst18|Dout[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clk clk~out0 add889:inst18|Dout[5] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}

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