mult13.vhd

来自「通过VHDL语言进行数字信号处理的FIR操作」· VHDL 代码 · 共 37 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mult13 is
PORT
( clk :  IN STD_LOGIC;
  Din :  IN SIGNED (8 DOWNTO 0);
 Dout :  OUT SIGNED (11 DOWNTO 0));
END mult13;
ARCHITECTURE a OF mult13 IS
SIGNAL s1 : SIGNED (11 DOWNTO 0);
SIGNAL s2 : SIGNED (10 DOWNTO 0);
SIGNAL s3 : SIGNED (11 DOWNTO 0);
SIGNAL s4 : SIGNED (11 DOWNTO 0);

BEGIN
P1:process(Din)
BEGIN
s1(11 DOWNTO 3)<=Din;
s1( 2 DOWNTO 0)<="000";
s2(10 DOWNTO 2)<=Din;
s2(1 DOWNTO 0)<="00";
if Din(8)='0' then 
s3<=('0'&s1(11 downto 1))+("00"&s2(10 DOWNTO 1))+("0000"&Din(8 DOWNTO 1));

else 
s3<=('1'&s1(11 downto 1))+("11"&s2(10 DOWNTO 1))+("1111"&Din(8 DOWNTO 1));

end if;
end process;
P2: PROCESS(clk)
BEGIN
if clk'event and clk='1' then
Dout<=s3;
end if;
END PROCESS;
END a;