sub131314.vhd

来自「通过VHDL语言进行数字信号处理的FIR操作」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
ENTITY sub131314 is
PORT(clk : in STD_LOGIC;
     Din1 :in signed (12 downto 0);
     Din2 :in signed (12 downto 0);
     Dout :out signed(13 downto 0));
END sub131314;
ARCHITECTURE a of sub131314 is
SIGNAL s1: signed(13 downto 0);
SIGNAL s2: signed(13 downto 0);
BEGIN
    s1<=(Din1(12)&Din1);
    s2<=(Din2(12)&Din2);
PROCESS(Din1,Din2,clk)
BEGIN
if clk'event and clk='1' then
Dout<=s2-s1;
end if;
end process;
end a;