hdefs.h

The Valgrind distribution has multiple tools. The most popular is the memory checking tool (called M

      Xsse_PACKSSD, Xsse_PACKSSW, Xsse_PACKUSW,
      Xsse_UNPCKHB, Xsse_UNPCKHW, Xsse_UNPCKHD, Xsse_UNPCKHQ,
      Xsse_UNPCKLB, Xsse_UNPCKLW, Xsse_UNPCKLD, Xsse_UNPCKLQ
   }
   X86SseOp;

extern HChar* showX86SseOp ( X86SseOp );


/* --------- */
typedef
   enum {
      Xin_Alu32R,    /* 32-bit mov/arith/logical, dst=REG */
      Xin_Alu32M,    /* 32-bit mov/arith/logical, dst=MEM */
      Xin_Sh32,      /* 32-bit shift/rotate, dst=REG */
      Xin_Test32,    /* 32-bit test of REG against imm32 (AND, set
                        flags, discard result) */
      Xin_Unary32,   /* 32-bit not and neg */
      Xin_MulL,      /* 32 x 32 -> 64 multiply */
      Xin_Div,       /* 64/32 -> (32,32) div and mod */
      Xin_Sh3232,    /* shldl or shrdl */
      Xin_Push,      /* push (32-bit?) value on stack */
      Xin_Call,      /* call to address in register */
      Xin_Goto,      /* conditional/unconditional jmp to dst */
      Xin_CMov32,    /* conditional move */
      Xin_LoadEX,    /* mov{s,z}{b,w}l from mem to reg */
      Xin_Store,     /* store 16/8 bit value in memory */
      Xin_Set32,     /* convert condition code to 32-bit value */
      Xin_Bsfr32,    /* 32-bit bsf/bsr */
      Xin_MFence,    /* mem fence (not just sse2, but sse0 and 1 too) */

      Xin_FpUnary,   /* FP fake unary op */
      Xin_FpBinary,  /* FP fake binary op */
      Xin_FpLdSt,    /* FP fake load/store */
      Xin_FpLdStI,   /* FP fake load/store, converting to/from Int */
      Xin_Fp64to32,  /* FP round IEEE754 double to IEEE754 single */
      Xin_FpCMov,    /* FP fake floating point conditional move */
      Xin_FpLdCW,    /* fldcw */
      Xin_FpStSW_AX, /* fstsw %ax */
      Xin_FpCmp,     /* FP compare, generating a C320 value into int reg */

      Xin_SseConst,  /* Generate restricted SSE literal */
      Xin_SseLdSt,   /* SSE load/store, no alignment constraints */
      Xin_SseLdzLO,  /* SSE load low 32/64 bits, zero remainder of reg */
      Xin_Sse32Fx4,  /* SSE binary, 32Fx4 */
      Xin_Sse32FLo,  /* SSE binary, 32F in lowest lane only */
      Xin_Sse64Fx2,  /* SSE binary, 64Fx2 */
      Xin_Sse64FLo,  /* SSE binary, 64F in lowest lane only */
      Xin_SseReRg,   /* SSE binary general reg-reg, Re, Rg */
      Xin_SseCMov,   /* SSE conditional move */
      Xin_SseShuf    /* SSE2 shuffle (pshufd) */
   }
   X86InstrTag;

/* Destinations are on the RIGHT (second operand) */

typedef
   struct {
      X86InstrTag tag;
      union {
         struct {
            X86AluOp op;
            X86RMI*  src;
            HReg     dst;
         } Alu32R;
         struct {
            X86AluOp  op;
            X86RI*    src;
            X86AMode* dst;
         } Alu32M;
         struct {
            X86ShiftOp op;
            UInt  src;  /* shift amount, or 0 means %cl */
            HReg  dst;
         } Sh32;
         struct {
            UInt imm32;
            HReg dst; /* not written, only read */
         } Test32;
         /* Not and Neg */
         struct {
            X86UnaryOp op;
            HReg       dst;
         } Unary32;
         /* EDX:EAX = EAX *s/u r/m32 */
         struct {
            Bool   syned;
            X86RM* src;
         } MulL;
         /* x86 div/idiv instruction.  Modifies EDX and EAX and reads src. */
         struct {
            Bool   syned;
            X86RM* src;
         } Div;
         /* shld/shrd.  op may only be Xsh_SHL or Xsh_SHR */
         struct {
            X86ShiftOp op;
            UInt       amt;   /* shift amount, or 0 means %cl */
            HReg       src;
            HReg       dst;
         } Sh3232;
         struct {
            X86RMI* src;
         } Push;
         /* Pseudo-insn.  Call target (an absolute address), on given
            condition (which could be Xcc_ALWAYS). */
         struct {
            X86CondCode cond;
            Addr32      target;
            Int         regparms; /* 0 .. 3 */
         } Call;
         /* Pseudo-insn.  Goto dst, on given condition (which could be
            Xcc_ALWAYS). */
         struct {
            IRJumpKind  jk;
            X86CondCode cond;
            X86RI*      dst;
         } Goto;
         /* Mov src to dst on the given condition, which may not
            be the bogus Xcc_ALWAYS. */
         struct {
            X86CondCode cond;
            X86RM*      src;
            HReg        dst;
         } CMov32;
         /* Sign/Zero extending loads.  Dst size is always 32 bits. */
         struct {
            UChar     szSmall;
            Bool      syned;
            X86AMode* src;
            HReg      dst;
         } LoadEX;
         /* 16/8 bit stores, which are troublesome (particularly
            8-bit) */
         struct {
            UChar     sz; /* only 1 or 2 */
            HReg      src;
            X86AMode* dst;
         } Store;
         /* Convert a x86 condition code to a 32-bit value (0 or 1). */
         struct {
            X86CondCode cond;
            HReg        dst;
         } Set32;
         /* 32-bit bsf or bsr. */
         struct {
            Bool isFwds;
            HReg src;
            HReg dst;
         } Bsfr32;
         /* Mem fence (not just sse2, but sse0 and 1 too).  In short,
            an insn which flushes all preceding loads and stores as
            much as possible before continuing.  On SSE2 we emit a
            real "mfence", on SSE1 "sfence ; lock addl $0,0(%esp)" and
            on SSE0 "lock addl $0,0(%esp)".  This insn therefore
            carries the host's hwcaps so the assembler knows what to
            emit. */
         struct {
            UInt hwcaps;
         } MFence;

         /* X86 Floating point (fake 3-operand, "flat reg file" insns) */
         struct {
            X86FpOp op;
            HReg    src;
            HReg    dst;
         } FpUnary;
         struct {
            X86FpOp op;
            HReg    srcL;
            HReg    srcR;
            HReg    dst;
         } FpBinary;
         struct {
            Bool      isLoad;
            UChar     sz; /* only 4 (IEEE single) or 8 (IEEE double) */
            HReg      reg;
            X86AMode* addr;
         } FpLdSt;
         /* Move 64-bit float to/from memory, converting to/from
            signed int on the way.  Note the conversions will observe
            the host FPU rounding mode currently in force. */
         struct {
            Bool      isLoad;
            UChar     sz; /* only 2, 4 or 8 */
            HReg      reg;
            X86AMode* addr;
         } FpLdStI;
         /* By observing the current FPU rounding mode, round (etc)
            src into dst given that dst should be interpreted as an
            IEEE754 32-bit (float) type. */
         struct {
            HReg src;
            HReg dst;
         } Fp64to32;
         /* Mov src to dst on the given condition, which may not
            be the bogus Xcc_ALWAYS. */
         struct {
            X86CondCode cond;
            HReg        src;
            HReg        dst;
         } FpCMov;
         /* Load the FPU's 16-bit control word (fldcw) */
         struct {
            X86AMode* addr;
         }
         FpLdCW;
         /* fstsw %ax */
         struct {
            /* no fields */
         }
         FpStSW_AX;
         /* Do a compare, generating the C320 bits into the dst. */
         struct {
            HReg    srcL;
            HReg    srcR;
            HReg    dst;
         } FpCmp;

         /* Simplistic SSE[123] */
         struct {
            UShort  con;
            HReg    dst;
         } SseConst;
         struct {
            Bool      isLoad;
            HReg      reg;
            X86AMode* addr;
         } SseLdSt;
         struct {
            UChar     sz; /* 4 or 8 only */
            HReg      reg;
            X86AMode* addr;
         } SseLdzLO;
         struct {
            X86SseOp op;
            HReg     src;
            HReg     dst;
         } Sse32Fx4;
         struct {
            X86SseOp op;
            HReg     src;
            HReg     dst;
         } Sse32FLo;
         struct {
            X86SseOp op;
            HReg     src;
            HReg     dst;
         } Sse64Fx2;
         struct {
            X86SseOp op;
            HReg     src;
            HReg     dst;
         } Sse64FLo;
         struct {
            X86SseOp op;
            HReg     src;
            HReg     dst;
         } SseReRg;
         /* Mov src to dst on the given condition, which may not
            be the bogus Xcc_ALWAYS. */
         struct {
            X86CondCode cond;
            HReg        src;
            HReg        dst;
         } SseCMov;
         struct {
            Int    order; /* 0 <= order <= 0xFF */
            HReg   src;
            HReg   dst;
         } SseShuf;

      } Xin;
   }
   X86Instr;

extern X86Instr* X86Instr_Alu32R    ( X86AluOp, X86RMI*, HReg );
extern X86Instr* X86Instr_Alu32M    ( X86AluOp, X86RI*,  X86AMode* );
extern X86Instr* X86Instr_Unary32   ( X86UnaryOp op, HReg dst );
extern X86Instr* X86Instr_Sh32      ( X86ShiftOp, UInt, HReg );
extern X86Instr* X86Instr_Test32    ( UInt imm32, HReg dst );
extern X86Instr* X86Instr_MulL      ( Bool syned, X86RM* );
extern X86Instr* X86Instr_Div       ( Bool syned, X86RM* );
extern X86Instr* X86Instr_Sh3232    ( X86ShiftOp, UInt amt, HReg src, HReg dst );
extern X86Instr* X86Instr_Push      ( X86RMI* );
extern X86Instr* X86Instr_Call      ( X86CondCode, Addr32, Int );
extern X86Instr* X86Instr_Goto      ( IRJumpKind, X86CondCode cond, X86RI* dst );
extern X86Instr* X86Instr_CMov32    ( X86CondCode, X86RM* src, HReg dst );
extern X86Instr* X86Instr_LoadEX    ( UChar szSmall, Bool syned,
                                      X86AMode* src, HReg dst );
extern X86Instr* X86Instr_Store     ( UChar sz, HReg src, X86AMode* dst );
extern X86Instr* X86Instr_Set32     ( X86CondCode cond, HReg dst );
extern X86Instr* X86Instr_Bsfr32    ( Bool isFwds, HReg src, HReg dst );
extern X86Instr* X86Instr_MFence    ( UInt hwcaps );

extern X86Instr* X86Instr_FpUnary   ( X86FpOp op, HReg src, HReg dst );
extern X86Instr* X86Instr_FpBinary  ( X86FpOp op, HReg srcL, HReg srcR, HReg dst );
extern X86Instr* X86Instr_FpLdSt    ( Bool isLoad, UChar sz, HReg reg, X86AMode* );
extern X86Instr* X86Instr_FpLdStI   ( Bool isLoad, UChar sz, HReg reg, X86AMode* );
extern X86Instr* X86Instr_Fp64to32  ( HReg src, HReg dst );
extern X86Instr* X86Instr_FpCMov    ( X86CondCode, HReg src, HReg dst );
extern X86Instr* X86Instr_FpLdCW    ( X86AMode* );
extern X86Instr* X86Instr_FpStSW_AX ( void );
extern X86Instr* X86Instr_FpCmp     ( HReg srcL, HReg srcR, HReg dst );

extern X86Instr* X86Instr_SseConst  ( UShort con, HReg dst );
extern X86Instr* X86Instr_SseLdSt   ( Bool isLoad, HReg, X86AMode* );
extern X86Instr* X86Instr_SseLdzLO  ( Int sz, HReg, X86AMode* );
extern X86Instr* X86Instr_Sse32Fx4  ( X86SseOp, HReg, HReg );
extern X86Instr* X86Instr_Sse32FLo  ( X86SseOp, HReg, HReg );
extern X86Instr* X86Instr_Sse64Fx2  ( X86SseOp, HReg, HReg );
extern X86Instr* X86Instr_Sse64FLo  ( X86SseOp, HReg, HReg );
extern X86Instr* X86Instr_SseReRg   ( X86SseOp, HReg, HReg );
extern X86Instr* X86Instr_SseCMov   ( X86CondCode, HReg src, HReg dst );
extern X86Instr* X86Instr_SseShuf   ( Int order, HReg src, HReg dst );


extern void ppX86Instr ( X86Instr*, Bool );

/* Some functions that insulate the register allocator from details
   of the underlying instruction set. */
extern void         getRegUsage_X86Instr ( HRegUsage*, X86Instr*, Bool );
extern void         mapRegs_X86Instr     ( HRegRemap*, X86Instr*, Bool );
extern Bool         isMove_X86Instr      ( X86Instr*, HReg*, HReg* );
extern Int          emit_X86Instr        ( UChar* buf, Int nbuf, X86Instr*, 
                                           Bool, void* dispatch );
extern X86Instr*    genSpill_X86         ( HReg rreg, Int offset, Bool );
extern X86Instr*    genReload_X86        ( HReg rreg, Int offset, Bool );
extern void         getAllocableRegs_X86 ( Int*, HReg** );
extern HInstrArray* iselBB_X86           ( IRBB*, VexArch, VexArchInfo* );

#endif /* ndef __LIBVEX_HOST_X86_HDEFS_H */

/*---------------------------------------------------------------*/
/*--- end                                    host-x86/hdefs.h ---*/
/*---------------------------------------------------------------*/