cpld_mpu1.vht

工程中使用的一段资源管理vhdl程序,有简单的分频代码

-- VHDL Test Bench Created from source file CPLD_MPU1.vhd -- 02/17/09  15:28:25
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Lattice recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "source->import"
-- menu in the ispLEVER Project Navigator to import the testbench.
-- Then edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE generics.components.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT CPLD_MPU1
	PORT(
		rst : IN std_logic;          
		BOE1 : OUT std_logic;
		BOE2 : OUT std_logic;
		BOE3 : OUT std_logic;
		BOE4 : OUT std_logic;
		BOE5 : OUT std_logic;
		BOE6 : OUT std_logic;
		BOE7 : OUT std_logic;
		BOE8 : OUT std_logic;
		BOE9 : OUT std_logic;
		BOE10 : OUT std_logic;
		BOE11 : OUT std_logic;
		BOE12 : OUT std_logic;
		BOE13 : OUT std_logic;
		BOE14 : OUT std_logic;
		BOE15 : OUT std_logic;
		BOE16 : OUT std_logic
		);
	END COMPONENT;

	SIGNAL BOE1 :  std_logic;
	SIGNAL BOE2 :  std_logic;
	SIGNAL BOE3 :  std_logic;
	SIGNAL BOE4 :  std_logic;
	SIGNAL BOE5 :  std_logic;
	SIGNAL BOE6 :  std_logic;
	SIGNAL BOE7 :  std_logic;
	SIGNAL BOE8 :  std_logic;
	SIGNAL BOE9 :  std_logic;
	SIGNAL BOE10 :  std_logic;
	SIGNAL BOE11 :  std_logic;
	SIGNAL BOE12 :  std_logic;
	SIGNAL BOE13 :  std_logic;
	SIGNAL BOE14 :  std_logic;
	SIGNAL BOE15 :  std_logic;
	SIGNAL BOE16 :  std_logic;
	SIGNAL rst :  std_logic;

BEGIN

	uut: CPLD_MPU1 PORT MAP(
		BOE1 => BOE1,
		BOE2 => BOE2,
		BOE3 => BOE3,
		BOE4 => BOE4,
		BOE5 => BOE5,
		BOE6 => BOE6,
		BOE7 => BOE7,
		BOE8 => BOE8,
		BOE9 => BOE9,
		BOE10 => BOE10,
		BOE11 => BOE11,
		BOE12 => BOE12,
		BOE13 => BOE13,
		BOE14 => BOE14,
		BOE15 => BOE15,
		BOE16 => BOE16,
		rst => rst
	);


-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      wait; -- will wait forever
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;