footpresure.lct

工程中使用的一段资源管理vhdl程序,有简单的分频代码

[Device]
Family = lc4k;
PartNumber = LC4128V-75T128I;
Package = 128TQFP;
PartType = LC4128V;
Speed = -7.5;
Operating_condition = IND;
Status = Production;
EN_PinGLB = yes;
EN_PinMacrocell = yes;

[Revision]
Parent = lc4k128v.lci;
DATE = 02/17/2009;
TIME = 15:35:37;
Source_Format = Pure_VHDL;
Synthesis = Synplify;

[Ignore Assignments]

[Clear Assignments]

[Backannotate Assignments]

[Global Constraints]

[Location Assignments]
layer = OFF;
BOE1 = Pin, 93, -, G, 0;
BOE2 = Pin, 92, -, G, 2;
BOE3 = Pin, 91, -, G, 4;
BOE4 = Pin, 90, -, G, 5;
BOE5 = Pin, 89, -, G, 6;
BOE6 = Pin, 86, -, G, 9;
BOE7 = Pin, 85, -, G, 10;
BOE8 = Pin, 84, -, G, 12;
BOE9 = Pin, 9, -, B, 6;
BOE10 = Pin, 28, -, C, 2;
BOE11 = Pin, 29, -, C, 0;
BOE12 = Pin, 20, -, C, 12;
BOE13 = Pin, 118, -, A, 2;
BOE14 = Pin, 117, -, A, 1;
BOE15 = Pin, 107, -, H, 5;
BOE16 = Pin, 106, -, H, 6;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]
NetList = VHDL;

[IO Types]
layer = OFF;
BOE1 = LVTTL, PIN, -, -;
BOE2 = LVTTL, PIN, 1, -;
BOE3 = LVTTL, PIN, 1, -;
BOE4 = LVTTL, PIN, 1, -;
BOE5 = LVTTL, PIN, 1, -;
BOE6 = LVTTL, PIN, 1, -;
BOE7 = LVTTL, PIN, 1, -;
BOE8 = LVTTL, PIN, 1, -;
BOE9 = LVTTL, PIN, 0, -;
BOE10 = LVTTL, PIN, 0, -;
BOE11 = LVTTL, PIN, 0, -;
BOE12 = LVTTL, PIN, 0, -;
BOE13 = LVTTL, PIN, 0, -;
BOE14 = LVTTL, PIN, 0, -;
BOE15 = LVTTL, PIN, 1, -;
BOE16 = LVTTL, PIN, 1, -;

[Pullup]

[Slewrate]
FAST = BOE1, BOE2, BOE3, BOE4, BOE5, BOE6, BOE7, BOE8, BOE9, BOE10, BOE11, BOE12, 
	BOE13, BOE14, BOE15, BOE16;

[Region]

[Timing Constraints]
layer = OFF;

[HSI Attributes]

[Input Delay]

[opt global constraints list]

[Explorer User Settings]

[Pin attributes list]

[global constraints list]

[Global Constraints Process Update]

[pin lock limitation]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[individual constraints list]

[Attributes list setting]

[Timing Analyzer]

[PLL Assignments]

[Dual Function Macrocell]

[Explorer Results]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[ORP Bypass]

[Register Powerup]

[Constraint Version]
version = 1.0;

[ORP ASSIGNMENTS]
layer = OFF;

[Node attribute]
layer = OFF;

[SYMBOL/MODULE attribute]
layer = OFF;

[Nodal Constraints]
layer = OFF;