cpld_mpu1.tlg

工程中使用的一段资源管理vhdl程序,有简单的分频代码

@N: CD630 :"E:\raflfile\sd\cpld\footvhdl.vhd":6:7:6:15|Synthesizing work.cpld_mpu1.archcpld_mpu1 
@W: CD638 :"E:\raflfile\sd\cpld\footvhdl.vhd":26:9:26:10|Signal c4 is undriven 
@W: CD638 :"E:\raflfile\sd\cpld\footvhdl.vhd":27:9:27:10|Signal c8 is undriven 
@W: CD638 :"E:\raflfile\sd\cpld\footvhdl.vhd":28:9:28:11|Signal nc4 is undriven 
@W: CD638 :"E:\raflfile\sd\cpld\footvhdl.vhd":29:9:29:11|Signal nc8 is undriven 
@W: CD638 :"E:\raflfile\sd\cpld\footvhdl.vhd":30:9:30:16|Signal exfio_d1 is undriven 
@W: CD638 :"E:\raflfile\sd\cpld\footvhdl.vhd":31:9:31:16|Signal exfio_d2 is undriven 
@W: CD638 :"E:\raflfile\sd\cpld\footvhdl.vhd":32:9:32:16|Signal exfio_d3 is undriven 
@W: CD638 :"E:\raflfile\sd\cpld\footvhdl.vhd":33:9:33:17|Signal excnt2048 is undriven 
Post processing for work.cpld_mpu1.archcpld_mpu1
@W: CL159 :"E:\raflfile\sd\cpld\footvhdl.vhd":12:3:12:7|Input reset is unused