readme.txt

Blakcfin processor Cache code example

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ADSP-BF535 EZ-KIT Lite Assembly based Cache

Analog Devices, Inc.
DSP Division
Three Technology Way
P.O. Box 9106
Norwood, MA 02062

Date Created:	1/30/02

This example shows how to configure the ADSP-BF535 to run with L1 memory
configured as cache.

Files contained in this directory:

readme.txt			this file
cache_example.asm		assembly file for cache example
cache_example.dpj		VisualDSP++ project file
cache_example.dxe		executable for this project
cache_example.ldf		linker description file 

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CONTENTS

I.	FUNCTION/ALGORITHM DESCRIPTION
II.	IMPLEMENTATION DESCRIPTION
III.	OPERATION DESCRIPTION       


I. FUNCTION/ALGORITHM DESCRIPTION

L1 Memory is configured as cache to run a simple blink program.


II.   IMPLEMENTATION DESCRIPTION

Since the cache-line valid bits come up in a random state at reset,
the first thing we need to do is clear each valid bit in both the data 
and instruction L1 caches.

The next thing we need to do is to set up the CPLBs for data and instruction 
memory.  The CPLB setup provided here is very basic.

Once CPLB's are defined, cache can be enabled.  There is a small blink program 
which is located in L2 memory.  This code is actually cached in this example.


III.  OPERATION DESCRIPTION

- Open the project "cache_example.dpj" in the VisualDSP Integrated Development and Debugger Environment (IDDE).
- Under the "Project" tab, select "Build Project".
- Open a ADSP-BF535 EZ-KIT Lite session in the Debugger.
- Load "cache_example.DXE" 
- Place breakpoints as desired to see the operation of the program.
- Focus on the ADSP-BF535 and select "RUN" from the menu bar.
- View the LEDs on the EZ-KIT Lite to see the blinking in action.