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vhdl语言写的基数分频器

# Reading C:/Modeltech_6.0/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0 Aug 19 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do clk_div3_tbw.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity clk_div3
# -- Compiling architecture behavioral of clk_div3
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity clk_div3_tbw
# -- Compiling architecture testbench_arch of clk_div3_tbw
# -- Compiling configuration clk_div3_cfg
# -- Loading entity clk_div3_tbw
# -- Loading architecture testbench_arch of clk_div3_tbw
# -- Loading entity clk_div3
# vsim -lib work -t 1ps clk_div3_tbw 
# Loading C:\Modeltech_6.0\win32/../std.standard
# Loading C:\Modeltech_6.0\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.0\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.0\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.0\win32/../std.textio(body)
# Loading C:\Modeltech_6.0\win32/../ieee.std_logic_textio(body)
# Loading work.clk_div3_tbw(testbench_arch)
# Loading work.clk_div3(behavioral)
# .wave
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Failure: Simulation successful (not a failure).  No problems detected. 
#    Time: 2160 ns  Iteration: 0  Process: /clk_div3_tbw/line__59 File: clk_div3_tbw.vhw
# Break at clk_div3_tbw.vhw line 97
# Simulation Breakpoint: Break at clk_div3_tbw.vhw line 97
# MACRO ./clk_div3_tbw.fdo PAUSED at line 13