decoder.edn

这是Actel 的FPGA的译码器的VHDL源代码。

(edif Decoder
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2008 7 10 13 38 46)
      (author "Synplicity, Inc.")
      (program "Synplify" (version "Version 9.0.2A2, mapper 9.0.2, Build 065R"))
     )
   )
  (library PA3
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell VCC (cellType GENERIC)
      (property dont_touch (string "false"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "1"))
 )
         )
       )
    )
    (cell OUTBUF (cellType GENERIC)
      (property preferred (string "true"))
      (property pad_cell (string "true"))
      (property dont_touch (string "false"))
       (view prim (viewType NETLIST)
         (interface
           (port PAD (direction OUTPUT)
           (property function (string "D"))
           (property is_pad (string "true"))
 )
           (port D (direction INPUT)
 )
         )
       )
    )
    (cell INBUF (cellType GENERIC)
      (property preferred (string "true"))
      (property pad_cell (string "true"))
      (property dont_touch (string "false"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "PAD"))
 )
           (port PAD (direction INPUT)
           (property is_pad (string "true"))
 )
         )
       )
    )
    (cell GND (cellType GENERIC)
      (property dont_touch (string "false"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "0"))
 )
         )
       )
    )
    (cell AND3C (cellType GENERIC)
      (property dont_touch (string "true"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "!A & !B & !C"))
 )
           (port A (direction INPUT)
 )
           (port B (direction INPUT)
 )
           (port C (direction INPUT)
 )
         )
        (property is_combinational (integer 1))
       )
    )
    (cell AND3B (cellType GENERIC)
      (property dont_touch (string "true"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "!A & !B & C"))
 )
           (port A (direction INPUT)
 )
           (port B (direction INPUT)
 )
           (port C (direction INPUT)
 )
         )
        (property is_combinational (integer 1))
       )
    )
    (cell AND3A (cellType GENERIC)
      (property dont_touch (string "false"))
       (view prim (viewType NETLIST)
         (interface
           (port Y (direction OUTPUT)
           (property function (string "!A & B & C"))
 )
           (port A (direction INPUT)
 )
           (port B (direction INPUT)
 )
           (port C (direction INPUT)
 )
         )
        (property is_combinational (integer 1))
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell Decoder (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port Data0 (direction INPUT))
           (port Data1 (direction INPUT))
           (port Enable (direction INPUT))
           (port (array (rename eq "Eq[3:0]") 4) (direction OUTPUT))
         )
         (contents
          (instance (rename Eq_pad_3 "Eq_pad[3]") (viewRef prim (cellRef OUTBUF (libraryRef PA3)))          )
          (instance (rename Eq_pad_2 "Eq_pad[2]") (viewRef prim (cellRef OUTBUF (libraryRef PA3)))          )
          (instance (rename Eq_pad_1 "Eq_pad[1]") (viewRef prim (cellRef OUTBUF (libraryRef PA3)))          )
          (instance (rename Eq_pad_0 "Eq_pad[0]") (viewRef prim (cellRef OUTBUF (libraryRef PA3)))          )
          (instance Enable_pad (viewRef prim (cellRef INBUF (libraryRef PA3)))
          )
          (instance Data1_pad (viewRef prim (cellRef INBUF (libraryRef PA3)))
          )
          (instance Data0_pad (viewRef prim (cellRef INBUF (libraryRef PA3)))
          )
          (instance AND3C_Eq_0_inst (viewRef prim (cellRef AND3C (libraryRef PA3)))
           (property is_instantiated (integer 1))
          )
          (instance AND3B_Eq_2_inst (viewRef prim (cellRef AND3B (libraryRef PA3)))
           (property is_instantiated (integer 1))
          )
          (instance AND3B_Eq_1_inst (viewRef prim (cellRef AND3B (libraryRef PA3)))
           (property is_instantiated (integer 1))
          )
          (instance AND3A_Eq_3_inst (viewRef prim (cellRef AND3A (libraryRef PA3)))
           (property is_instantiated (integer 1))
          )
          (instance VCC_i (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (instance VCC_i_0 (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i_0 (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (net GND (joined
           (portRef Y (instanceRef GND_i))
          ))
          (net VCC (joined
           (portRef Y (instanceRef VCC_i))
          ))
          (net Data0_c (joined
           (portRef Y (instanceRef Data0_pad))
           (portRef B (instanceRef AND3A_Eq_3_inst))
           (portRef C (instanceRef AND3B_Eq_1_inst))
           (portRef B (instanceRef AND3B_Eq_2_inst))
           (portRef B (instanceRef AND3C_Eq_0_inst))
          ))
          (net Data0 (joined
           (portRef Data0)
           (portRef PAD (instanceRef Data0_pad))
          ))
          (net Data1_c (joined
           (portRef Y (instanceRef Data1_pad))
           (portRef C (instanceRef AND3A_Eq_3_inst))
           (portRef A (instanceRef AND3B_Eq_1_inst))
           (portRef C (instanceRef AND3B_Eq_2_inst))
           (portRef A (instanceRef AND3C_Eq_0_inst))
          ))
          (net Data1 (joined
           (portRef Data1)
           (portRef PAD (instanceRef Data1_pad))
          ))
          (net Enable_c (joined
           (portRef Y (instanceRef Enable_pad))
           (portRef A (instanceRef AND3A_Eq_3_inst))
           (portRef B (instanceRef AND3B_Eq_1_inst))
           (portRef A (instanceRef AND3B_Eq_2_inst))
           (portRef C (instanceRef AND3C_Eq_0_inst))
          ))
          (net Enable (joined
           (portRef Enable)
           (portRef PAD (instanceRef Enable_pad))
          ))
          (net (rename Eq_1_c_0 "Eq_1_c[0]") (joined
           (portRef Y (instanceRef AND3C_Eq_0_inst))
           (portRef D (instanceRef Eq_pad_0))
          ))
          (net (rename Eq_0 "Eq[0]") (joined
           (portRef PAD (instanceRef Eq_pad_0))
           (portRef (member eq 3))
          ))
          (net (rename Eq_1_c_1 "Eq_1_c[1]") (joined
           (portRef Y (instanceRef AND3B_Eq_1_inst))
           (portRef D (instanceRef Eq_pad_1))
          ))
          (net (rename Eq_1 "Eq[1]") (joined
           (portRef PAD (instanceRef Eq_pad_1))
           (portRef (member eq 2))
          ))
          (net (rename Eq_1_c_2 "Eq_1_c[2]") (joined
           (portRef Y (instanceRef AND3B_Eq_2_inst))
           (portRef D (instanceRef Eq_pad_2))
          ))
          (net (rename Eq_2 "Eq[2]") (joined
           (portRef PAD (instanceRef Eq_pad_2))
           (portRef (member eq 1))
          ))
          (net (rename Eq_1_c_3 "Eq_1_c[3]") (joined
           (portRef Y (instanceRef AND3A_Eq_3_inst))
           (portRef D (instanceRef Eq_pad_3))
          ))
          (net (rename Eq_3 "Eq[3]") (joined
           (portRef PAD (instanceRef Eq_pad_3))
           (portRef (member eq 0))
          ))
          (net (rename GNDZ0 "GND") (joined
           (portRef Y (instanceRef GND_i_0))
          ))
          (net (rename VCCZ0 "VCC") (joined
           (portRef Y (instanceRef VCC_i_0))
          ))
         )
       )
    )
  )
  (design Decoder (cellRef Decoder (libraryRef work)))
)