decoder.sdf

这是Actel 的FPGA的译码器的VHDL源代码。

(DELAYFILE
(SDFVERSION "OVI 2.1")
(DESIGN "Decoder")
(DATE "123")
(VENDOR "ProASIC3")
(PROGRAM "Synplify")
(VERSION "9.0.2, Build 065R")
(DIVIDER /)
(VOLTAGE 2.500000:2.500000:2.500000)
(PROCESS "TYPICAL")
(TEMPERATURE 70.000000:70.000000:70.000000)
(TIMESCALE 1ns)
(CELL
  (CELLTYPE "Decoder")
  (INSTANCE)
  (TIMINGCHECK

  )
)
)