decoder_top.tlg

来自「这是Actel 的FPGA的译码器的VHDL源代码。」· TLG 代码 · 共 20 行

Selecting top level module decoder_top
@N: CG364 :"E:\programme\Decoder\hdl\KEY.v":21:7:21:9|Synthesizing module KEY

@N: CG364 :"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v":1864:7:1864:9|Synthesizing module VCC

@N: CG364 :"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v":1163:7:1163:9|Synthesizing module GND

@N: CG364 :"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v":1374:7:1374:12|Synthesizing module NAND3A

@N: CG364 :"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v":1386:7:1386:12|Synthesizing module NAND3C

@N: CG364 :"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v":1380:7:1380:12|Synthesizing module NAND3B

@N: CG364 :"E:\programme\Decoder\smartgen\Decoder\Decoder.v":5:7:5:13|Synthesizing module Decoder

@N: CG364 :"E:\programme\Decoder\component\work\decoder_top\decoder_top.v":5:7:5:17|Synthesizing module decoder_top

@W: CL168 :"E:\programme\Decoder\component\work\decoder_top\decoder_top.v":20:8:20:10|Pruning instance VCC - not in use ...