decoder_top.areasrr

来自「这是Actel 的FPGA的译码器的VHDL源代码。」· AREASRR 代码 · 共 37 行

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Report for cell decoder_top.verilog
                                          Cell usage:
                               cell       count     area    count*area
                            Decoder         1       4.0        4.0
                                GND         1       0.0        0.0
                              INBUF         3       0.0        0.0
                                KEY         1      14.0       14.0
                             OUTBUF         4       0.0        0.0
                                VCC         1       0.0        0.0
                            
                         TOTAL             11                 18.0
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Report for cell Decoder.netlist
     Instance path:  Decoder_0
                                          Cell usage:
                               cell       count     area    count*area
                                GND         1       0.0        0.0
                             NAND3A         1       1.0        1.0
                             NAND3B         2       1.0        2.0
                             NAND3C         1       1.0        1.0
                                VCC         1       0.0        0.0
                            
                         TOTAL              6                  4.0
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Report for cell KEY.netlist
     Instance path:  KEY_0
                                          Cell usage:
                               cell       count     area    count*area
                               DFN1        10       1.0       10.0
                                GND         1       0.0        0.0
                              NOR3C         2       1.0        2.0
                               OR3C         2       1.0        2.0
                                VCC         1       0.0        0.0
                            
                         TOTAL             16                 14.0