decoder_top.srr

这是Actel 的FPGA的译码器的VHDL源代码。

#Build: Synplify Pro 9.0.2A2, Build 250R, Feb 20 2008
#install: D:\Libero\Synplify\synplify_902A2
#OS: Windows XP 5.1
#Hostname: BIMINGMING

#Implementation: synthesis

#Mon Aug 18 15:06:24 2008

$ Start of Compile
#Mon Aug 18 15:06:24 2008

Synplicity Verilog Compiler, version 1.0, Build 145R, built Mar  5 2008
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved

@I::"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v"
@I::"E:\programme\Decoder\hdl\KEY.v"
@I::"E:\programme\Decoder\smartgen\Decoder\Decoder.v"
@I::"E:\programme\Decoder\component\work\decoder_top\decoder_top.v"
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module decoder_top
@N: CG364 :"E:\programme\Decoder\hdl\KEY.v":21:7:21:9|Synthesizing module KEY

@N: CG364 :"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v":1864:7:1864:9|Synthesizing module VCC

@N: CG364 :"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v":1163:7:1163:9|Synthesizing module GND

@N: CG364 :"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v":1374:7:1374:12|Synthesizing module NAND3A

@N: CG364 :"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v":1386:7:1386:12|Synthesizing module NAND3C

@N: CG364 :"D:\Libero\Synplify\synplify_902A2\lib\proasic\proasic3.v":1380:7:1380:12|Synthesizing module NAND3B

@N: CG364 :"E:\programme\Decoder\smartgen\Decoder\Decoder.v":5:7:5:13|Synthesizing module Decoder

@N: CG364 :"E:\programme\Decoder\component\work\decoder_top\decoder_top.v":5:7:5:17|Synthesizing module decoder_top

@W: CL168 :"E:\programme\Decoder\component\work\decoder_top\decoder_top.v":20:8:20:10|Pruning instance VCC - not in use ...

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Aug 18 15:06:24 2008

###########################################################]
Synplicity Proasic Technology Mapper, Version 9.0.2, Build 065R, Built Mar  5 2008 17:44:07
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved
Product Version Version 9.0.2A2
@N: MF249 |Running in 32-bit mode.
@N: MF258 |Gated clock conversion disabled 


Automatic dissolve at startup in view:work.decoder_top(verilog) of Decoder_0(Decoder)
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 40MB peak: 40MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 40MB peak: 40MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 40MB peak: 41MB)

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 39MB peak: 41MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 39MB peak: 41MB)

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 39MB peak: 41MB)
Writing Analyst data base E:\programme\Decoder\synthesis\decoder_top.srm
@N: BN225 |Writing default property annotation file E:\programme\Decoder\synthesis\decoder_top.map.
Writing EDIF Netlist and constraint files
Version 9.0.2A2
Found clock decoder_top|sysclk with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Aug 18 15:06:28 2008
#


Top view:               decoder_top
Library name:           PA3
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.42, P = 1.30, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        proasic3
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 7.321

                       Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock         Frequency     Frequency     Period        Period        Slack     Type         Group              
-------------------------------------------------------------------------------------------------------------------------
decoder_top|sysclk     100.0 MHz     373.3 MHz     10.000        2.679         7.321     inferred     Inferred_clkgroup_0
=========================================================================================================================





Clock Relationships
*******************

Clocks                                  |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------
Starting            Ending              |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------
decoder_top|sysclk  decoder_top|sysclk  |  10.000      7.321  |  No paths    -      |  No paths    -      |  No paths    -    
==============================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: decoder_top|sysclk
====================================



Starting Points with Worst Slack
********************************

                     Starting                                               Arrival          
Instance             Reference              Type     Pin     Net            Time        Slack
                     Clock                                                                   
---------------------------------------------------------------------------------------------
KEY_0.key_temp13     decoder_top|sysclk     DFN1     Q       key_temp13     0.550       7.321
KEY_0.key_temp23     decoder_top|sysclk     DFN1     Q       key_temp23     0.550       7.321
KEY_0.key_temp14     decoder_top|sysclk     DFN1     Q       key_temp14     0.550       7.502
KEY_0.key_temp24     decoder_top|sysclk     DFN1     Q       key_temp24     0.550       7.502
KEY_0.key_temp11     decoder_top|sysclk     DFN1     Q       key_temp11     0.550       8.066
KEY_0.key_temp21     decoder_top|sysclk     DFN1     Q       key_temp21     0.550       8.066
KEY_0.key_temp12     decoder_top|sysclk     DFN1     Q       key_temp12     0.550       8.173
KEY_0.key_temp22     decoder_top|sysclk     DFN1     Q       key_temp22     0.550       8.173
=============================================================================================


Ending Points with Worst Slack
******************************

                     Starting                                                     Required          
Instance             Reference              Type     Pin     Net                  Time         Slack
                     Clock                                                                          
----------------------------------------------------------------------------------------------------
KEY_0.key_out1       decoder_top|sysclk     DFN1     D       un1_key_out1_i_0     9.598        7.321
KEY_0.key_out2       decoder_top|sysclk     DFN1     D       un1_key_out2_i_0     9.598        7.321
KEY_0.key_temp12     decoder_top|sysclk     DFN1     D       key_temp11           9.572        8.733
KEY_0.key_temp13     decoder_top|sysclk     DFN1     D       key_temp12           9.572        8.733
KEY_0.key_temp14     decoder_top|sysclk     DFN1     D       key_temp13           9.572        8.733
KEY_0.key_temp22     decoder_top|sysclk     DFN1     D       key_temp21           9.572        8.733
KEY_0.key_temp23     decoder_top|sysclk     DFN1     D       key_temp22           9.572        8.733
KEY_0.key_temp24     decoder_top|sysclk     DFN1     D       key_temp23           9.572        8.733
====================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        10.000
    - Setup time:                            0.402
    = Required time:                         9.598

    - Propagation time:                      2.277
    = Slack (critical) :                     7.321

    Number of logic level(s):                2
    Starting point:                          KEY_0.key_temp13 / Q
    Ending point:                            KEY_0.key_out1 / D
    The start point is clocked by            decoder_top|sysclk [rising] on pin CLK
    The end   point is clocked by            decoder_top|sysclk [rising] on pin CLK

Instance / Net                     Pin      Pin               Arrival     No. of    
Name                     Type      Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
KEY_0.key_temp13         DFN1      Q        Out     0.550     0.550       -         
key_temp13               Net       -        -       0.288     -           2         
KEY_0.un1_key_out1_2     NOR3C     C        In      -         0.839       -         
KEY_0.un1_key_out1_2     NOR3C     Y        Out     0.479     1.317       -         
un1_key_out1_2           Net       -        -       0.240     -           1         
KEY_0.un1_key_out1       OR3C      C        In      -         1.558       -         
KEY_0.un1_key_out1       OR3C      Y        Out     0.479     2.036       -         
un1_key_out1_i_0         Net       -        -       0.240     -           1         
KEY_0.key_out1           DFN1      D        In      -         2.277       -         
====================================================================================
Total path delay (propagation time + setup) of 2.679 is 1.910(71.3%) logic and 0.768(28.7%) route.



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Report for cell decoder_top.verilog
  Core Cell usage:
              cell count     area count*area
               GND     3      0.0        0.0
            NAND3A     1      1.0        1.0
            NAND3B     2      1.0        2.0
            NAND3C     1      1.0        1.0
             NOR3C     2      1.0        2.0
              OR3C     2      1.0        2.0
               VCC     3      0.0        0.0


              DFN1    10      1.0       10.0
                   -----          ----------
             TOTAL    24                18.0


  IO Cell usage:
              cell count
             INBUF     3
            OUTBUF     4
                   -----
             TOTAL     7


Core Cells         : 18 of 384 (5%)
IO Cells           : 7 of 49 (14%)
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Aug 18 15:06:28 2008

###########################################################]

Total runtime: 00h:00m:04s realtime