decoder.areasrr

来自「这是Actel 的FPGA的译码器的VHDL源代码。」· AREASRR 代码 · 共 14 行

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Report for cell Decoder.verilog
                                          Cell usage:
                               cell       count     area    count*area
                              AND3A         1       1.0        1.0
                              AND3B         2       1.0        2.0
                              AND3C         1       1.0        1.0
                                GND         1       0.0        0.0
                              INBUF         3       0.0        0.0
                             OUTBUF         4       0.0        0.0
                                VCC         1       0.0        0.0
                            
                         TOTAL             13                  4.0