decoder.tlg

这是Actel 的FPGA的译码器的VHDL源代码。

Selecting top level module Decoder
@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":26:7:26:11|Synthesizing module AND3A

@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":32:7:32:11|Synthesizing module AND3B

@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":38:7:38:11|Synthesizing module AND3C

@N: CG364 :"E:\Easy FPGA030\Decoder\smartgen\Decoder\Decoder.v":5:7:5:13|Synthesizing module Decoder