decoder_top.msg

这是Actel 的FPGA的译码器的VHDL源代码。

@TM:1215653367
@N: BN225 :"":0:0:0:-1|Writing default property annotation file E:\Easy FPGA030\Decoder\synthesis\decoder_top.map.
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@N: MT320 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT322 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1215670686
@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":26:7:26:11|Synthesizing module AND3A
@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":32:7:32:11|Synthesizing module AND3B
@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":38:7:38:11|Synthesizing module AND3C
@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":1163:7:1163:9|Synthesizing module GND
@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":1864:7:1864:9|Synthesizing module VCC
@N: CG364 :"E:\Easy FPGA030\Decoder\component\work\decoder_top\decoder_top.v":5:7:5:17|Synthesizing module decoder_top
@W: CL168 :"E:\Easy FPGA030\Decoder\component\work\decoder_top\decoder_top.v":20:8:20:10|M
@N: CG364 :"E:\Easy FPGA030\Decoder\hdl\KEY.v":2:7:2:9|Synthesizing module KEY
@N: CG364 :"E:\Easy FPGA030\Decoder\smartgen\Decoder\Decoder.v":5:7:5:13|Synthesizing module Decoder