decoder.msg

来自「这是Actel 的FPGA的译码器的VHDL源代码。」· MSG 代码 · 共 10 行

@TM:1215594643
@N: BN225 :"":0:0:0:-1|Writing default property annotation file E:\Easy FPGA030\Decoder\synthesis\Decoder.map.
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@N: MT320 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT322 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":26:7:26:11|Synthesizing module AND3A
@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":32:7:32:11|Synthesizing module AND3B
@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":38:7:38:11|Synthesizing module AND3C
@N: CG364 :"E:\Easy FPGA030\Decoder\smartgen\Decoder\Decoder.v":5:7:5:13|Synthesizing module Decoder