decoder.srr

这是Actel 的FPGA的译码器的VHDL源代码。

#Build: Synplify 9.0.2A2, Build 250R, Feb 20 2008
#install: C:\Libero\Synplify\Synplify_902A2
#OS: Windows XP 5.1
#Hostname: JIANGYICHENG

#Implementation: synthesis

#Thu Jul 10 13:38:45 2008

$ Start of Compile
#Thu Jul 10 13:38:45 2008

Synplicity Verilog Compiler, version 1.0, Build 145R, built Mar  5 2008
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved

@I::"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v"
@I::"E:\Easy FPGA030\Decoder\smartgen\Decoder\Decoder.v"
Verilog syntax check successful!

Compiler output is up to date.  No re-compile necessary

Selecting top level module Decoder
@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":26:7:26:11|Synthesizing module AND3A

@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":32:7:32:11|Synthesizing module AND3B

@N: CG364 :"C:\Libero\Synplify\Synplify_902A2\lib\proasic\proasic3.v":38:7:38:11|Synthesizing module AND3C

@N: CG364 :"E:\Easy FPGA030\Decoder\smartgen\Decoder\Decoder.v":5:7:5:13|Synthesizing module Decoder

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jul 10 13:38:45 2008

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Synplicity Proasic Technology Mapper, Version 9.0.2, Build 065R, Built Mar  5 2008 17:44:07
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved
Product Version Version 9.0.2A2
@N: MF249 |Running in 32-bit mode.


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 40MB peak: 40MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 40MB)
Writing Analyst data base E:\Easy FPGA030\Decoder\synthesis\Decoder.srm
@N: BN225 |Writing default property annotation file E:\Easy FPGA030\Decoder\synthesis\Decoder.map.
Writing EDIF Netlist and constraint files
Version 9.0.2A2


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jul 10 13:38:46 2008
#


Top view:               Decoder
Library name:           PA3
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.42, P = 1.30, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        proasic3
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Report for cell Decoder.verilog
  Core Cell usage:
              cell count     area count*area
             AND3A     1      1.0        1.0
             AND3B     2      1.0        2.0
             AND3C     1      1.0        1.0
               GND     1      0.0        0.0
               VCC     1      0.0        0.0


                   -----          ----------
             TOTAL     6                 4.0


  IO Cell usage:
              cell count
             INBUF     3
            OUTBUF     4
                   -----
             TOTAL     7


Core Cells         : 4 of 384 (1%)
IO Cells           : 7 of 49 (14%)
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jul 10 13:38:46 2008

###########################################################]

Total runtime: 00h:00m:01s realtime