decoder_top_sdc.sdc

这是Actel 的FPGA的译码器的VHDL源代码。

# Top Level Design Parameters

# Clocks

create_clock -period 10.000000 -waveform {0.000000 5.000000} sysclk

# False Paths Between Clocks


# False Path Constraints


# Maximum Delay Constraints


# Multicycle Constraints


# Virtual Clocks
# Output Load Constraints
# Driving Cell Constraints
# Wire Loads
# set_wire_load_mode top

# Other Constraints