decoder_top.cxf

这是Actel 的FPGA的译码器的VHDL源代码。

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>decoder_top</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./decoder_top.sdb</name><fileType><userFileType type="SDB"/></fileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="1"><name>./decoder_top.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SmartDesign</category><function>SmartDesign</function><variation>SmartDesign</variation><vendor/><version/><vendorExtension><type>SMARTDESIGN</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><model><signals><signal><name>key_in1</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>key_in2</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>sysclk</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>Eq</name><direction>out</direction><left>3</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>