modelsim.ini

来自「这是Actel 的FPGA的译码器的VHDL源代码。」· INI 代码 · 共 21 行

[Library]
others = $MODEL_TECH/../modelsim.ini
proasic3 = D:/Libero/Designer/lib/modelsim/precompiled/vlog/proasic3










syncad_vhdl_lib = D:\Libero\Designer/lib/actel/syncad_vhdl_lib

[vcom]
VHDL93 = 1

[vsim]
IterationLimit = 5000