decoder.cxf

这是Actel 的FPGA的译码器的VHDL源代码。

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>Decoder</name><vendor/><library/><version/><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>Decoder.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="OTHER_FILESET"><file fileid="1"><name>Decoder.gen</name><fileType><userFileType type="GEN"/></fileType></file><file fileid="2"><name>Decoder.log</name><fileType><userFileType type="LOG"/></fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>OTHER_FILESET</fileSetRef><name>OTHER</name></view></views></hwModel><category>Decoder</category><function>Decoder</function><variation>Decoder</variation><vendor/><version>2.0</version><model><signals><signal><name>Data0</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>Data1</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>Enable</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>Eq</name><direction>out</direction><left>3</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>