decoder.gen

来自「这是Actel 的FPGA的译码器的VHDL源代码。」· GEN 代码 · 共 19 行

Version:8.3.0.22
ACTGENU_CALL:1
BATCH:T
FAM:ProASIC3
OUTFORMAT:Verilog
LPMTYPE:LPM_DECODE
LPM_HINT:PndgenDecode
INSERT_PAD:NO
INSERT_IOREG:NO
GEN_BHV_VHDL_VAL:F
GEN_BHV_VERILOG_VAL:F
MGNTIMER:F
MGNCMPL:T
"DESDIR:E:/Easy FPGA030/Decoder/smartgen\Decoder"
GEN_BEHV_MODULE:T
 DECODES:4
 EN_POLARITY:0
 EQ_POLARITY:0