decoder.v

来自「这是Actel 的FPGA的译码器的VHDL源代码。」· Verilog 代码 · 共 47 行

`timescale 1 ns/100 ps
// Version: 8.3 8.3.0.22


module Decoder(Data0,Data1,Enable,Eq);
input Data0, Data1, Enable;
output [3:0] Eq;

    
    NAND3A NAND3A_Eq_3_inst(.A(Enable), .B(Data0), .C(Data1), .Y(
        Eq[3]));
    NAND3C NAND3C_Eq_0_inst(.A(Data1), .B(Data0), .C(Enable), .Y(
        Eq[0]));
    NAND3B NAND3B_Eq_1_inst(.A(Data1), .B(Enable), .C(Data0), .Y(
        Eq[1]));
    NAND3B NAND3B_Eq_2_inst(.A(Enable), .B(Data0), .C(Data1), .Y(
        Eq[2]));
    
endmodule

// _Disclaimer: Please leave the following comments in the file, they are for internal purposes only._


// _GEN_File_Contents_

// Version:8.3.0.22
// ACTGENU_CALL:1
// BATCH:T
// FAM:ProASIC3
// OUTFORMAT:Verilog
// LPMTYPE:LPM_DECODE
// LPM_HINT:PndgenDecode
// INSERT_PAD:NO
// INSERT_IOREG:NO
// GEN_BHV_VHDL_VAL:F
// GEN_BHV_VERILOG_VAL:F
// MGNTIMER:F
// MGNCMPL:T
// "DESDIR:E:/Easy FPGA030/Decoder/smartgen\Decoder"
// GEN_BEHV_MODULE:T
//  DECODES:4
//  EN_POLARITY:0
//  EQ_POLARITY:0

// _End_Comments_