smartgen.aws

这是Actel 的FPGA的译码器的VHDL源代码。

<?xml version="1.0" encoding="UTF-8" standalone="no" ?><workspace xmlns="http://actel.com/sweng/afi"><name>smartgen</name><netlistFormat>Verilog</netlistFormat><reports><resource select="T"/></reports><subproject libero="T"/><hdltype>Verilog</hdltype><componentInstances/><component name="Decoder::work"/><component name="decoder_top::work"/><component name="KEY::work"/><device die="" family="ProASIC3" package=""/><SmartGen version="8.0"/></workspace>