dds_lut.v

利用FPGA实现DDS经过编译没有错误。编译环境为QuartusII7.2

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
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// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module dds_lut(
	wren,
	rden,
	wrclock,
	clk,
	data,
	phasein,
	select,
	wraddress,
	daoutput
);

input	wren;
input	rden;
input	wrclock;
input	clk;
input	[15:0] data;
input	[11:0] phasein;
input	[1:0] select;
input	[8:0] wraddress;
output	[11:0] daoutput;

wire	[15:0] ram_data;
wire	[11:0] SYNTHESIZED_WIRE_0;
wire	[11:0] SYNTHESIZED_WIRE_1;
wire	[11:0] SYNTHESIZED_WIRE_2;





sin_rom	b2v_inst(.clock(clk),
.address(phasein),.q(SYNTHESIZED_WIRE_2));

cos_rom	b2v_inst1(.clock(clk),
.address(phasein),.q(SYNTHESIZED_WIRE_1));

square	b2v_inst2(.clock(clk),
.address(phasein),.q(SYNTHESIZED_WIRE_0));

mux4	b2v_inst3(.data0x(ram_data[11:0]),
.data1x(SYNTHESIZED_WIRE_0),.data2x(SYNTHESIZED_WIRE_1),.data3x(SYNTHESIZED_WIRE_2),.sel(select),.result(daoutput));

ram	b2v_inst7(.wren(wren),
.rden(rden),.wrclock(wrclock),.rdclock(clk),.data(data),.rdaddress(phasein[11:3]),.wraddress(wraddress),.q(ram_data));


endmodule