div_mult.v

来自「用fpga+usb显现的4通道800K的数据采集方案」· Verilog 代码 · 共 23 行

module div_mult(clk,div512,div256,div128,div64,div32,div16,div8,div4,div2);

input clk;
output div2,div4,div8,div16,div32,div64,div128,div256,div512;

reg[8:0] counter;//64.32.16.8.4.2分频
always@(posedge clk)
begin
  counter<=counter+7'b0000_001;
end
assign div512=~counter[8];
assign div256=~counter[7];
assign div128=~counter[6];
assign div64=~counter[5];
assign div32=~counter[4];
assign div16=~counter[3];
assign div8=~counter[2];
assign div4=~counter[1];
assign div2=~counter[0];


endmodule