div5.v

来自「用fpga+usb显现的4通道800K的数据采集方案」· Verilog 代码 · 共 33 行

module div5(clk,clk_out);

  input clk;
  output clk_out;
  //output c1,c2;
  reg[2:0] state;
  reg clk1;
    always @(posedge clk)// or negedge reset)
      //if(!reset)
        // state<=3'b000;
      //else
        case(state)
          3'b000:state<=3'b001;
          3'b001:state<=3'b011;
          3'b011:state<=3'b101;
          3'b101:state<=3'b110;
          3'b110:state<=3'b000;
          default:state<=3'b000;
        endcase

always @(negedge clk)// or negedge reset)
      //if(!reset)
         //clk1<=1'b0;
      //else
begin
   clk1<=state[0];
end

  //assign c1=state[0];
  //assign c2=clk1;
  assign clk_out=state[0]&clk1;
endmodule