ch8_matrix.tan.rpt

用fpga+usb显现的4通道800K的数据采集方案

; Device Name                                           ; EP2C70F896C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK_40M         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK_40M'                                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------+-----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                              ; To                                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------+-----------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 26.64 MHz ( period = 37.540 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_Get[3]  ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.656 ns                ;
; N/A                                     ; 26.64 MHz ( period = 37.540 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_Get[1]  ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.656 ns                ;
; N/A                                     ; 26.64 MHz ( period = 37.540 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_Get[2]  ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.656 ns                ;
; N/A                                     ; 26.64 MHz ( period = 37.540 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_Get[0]  ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.656 ns                ;
; N/A                                     ; 27.10 MHz ( period = 36.902 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_Get[4]  ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.338 ns                ;
; N/A                                     ; 27.11 MHz ( period = 36.882 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_AD[4]   ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; 27.11 MHz ( period = 36.882 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_AD[3]   ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; 27.11 MHz ( period = 36.882 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_AD[2]   ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; 27.11 MHz ( period = 36.882 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_AD[1]   ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; 27.11 MHz ( period = 36.882 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_AD[0]   ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.332 ns                ;
; N/A                                     ; 27.24 MHz ( period = 36.706 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_SLWR[2] ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.239 ns                ;
; N/A                                     ; 27.24 MHz ( period = 36.706 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_SLWR[0] ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.239 ns                ;
; N/A                                     ; 27.24 MHz ( period = 36.706 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_SLWR[1] ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 3.239 ns                ;
; N/A                                     ; 27.68 MHz ( period = 36.128 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_SLWR[3] ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 2.951 ns                ;
; N/A                                     ; 27.68 MHz ( period = 36.126 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_small_SLWR[4] ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 2.950 ns                ;
; N/A                                     ; 28.60 MHz ( period = 34.964 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_big[7]        ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 2.359 ns                ;
; N/A                                     ; 28.60 MHz ( period = 34.964 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_big[6]        ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 2.359 ns                ;
; N/A                                     ; 28.60 MHz ( period = 34.964 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_big[2]        ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 2.359 ns                ;
; N/A                                     ; 28.60 MHz ( period = 34.964 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_big[5]        ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 2.359 ns                ;
; N/A                                     ; 28.60 MHz ( period = 34.964 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_big[1]        ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 2.359 ns                ;
; N/A                                     ; 28.60 MHz ( period = 34.964 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_big[0]        ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 2.359 ns                ;
; N/A                                     ; 28.60 MHz ( period = 34.964 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_big[8]        ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 2.359 ns                ;
; N/A                                     ; 28.60 MHz ( period = 34.964 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_big[4]        ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 2.359 ns                ;
; N/A                                     ; 28.60 MHz ( period = 34.964 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_big[3]        ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 2.359 ns                ;
; N/A                                     ; 28.63 MHz ( period = 34.930 ns )                    ; my_DFF:inst13|Q                   ; gating_pulse:inst|counter_big[14]       ; CLK_40M    ; CLK_40M  ; None                        ; None                      ; 2.347 ns                ;