wait2s.v

来自「用fpga+usb显现的4通道800K的数据采集方案」· Verilog 代码 · 共 82 行

module wait2s(CLK,flag,W);
input CLK,flag;
output W;
reg W;
reg temp_W;
reg[10:0] counter;

always@(posedge CLK)
begin
  if(flag)
    begin
       if(counter==1151)counter<=11'b0;//周期是21.14ms*(1024+128)
       else counter<=counter+11'b1;
    end
  else
    begin
     counter<=11'b0;
    end 
end

always@(counter or flag)
begin
 if(flag)
   begin
    if((counter>=0)&&(counter<=1023))temp_W=1;
    else temp_W=0;
   end
 else
  begin
    temp_W=0;
  end
end

always@(posedge CLK)
begin
  W<=temp_W;
end

endmodule

/*
module wait2s(flag,CLK,W);
input flag,CLK;
output W;
reg W;
reg temp_W;
reg[2:0] counter;

always@(posedge CLK)
begin
  if(flag)
    begin
       if(counter==6)counter<=0;//周期是21.14ms*(1024+128)
       else counter<=counter+1;
    end
  else
    begin
     counter<=0;
    end 
end

always@(counter or flag)
begin
 if(flag)
   begin
    if((counter>=0)&&(counter<=1))temp_W=1;
    else temp_W=0;
   end
 else
  begin
    temp_W=0;
  end
end

always@(posedge CLK)
begin
  W<=temp_W;
end

endmodule
*/