📄 ch8_matrix.map.rpt
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------+
; |CH8_Matrix ; 123 (3) ; 84 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CH8_Matrix ;
; |div5:inst19| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CH8_Matrix|div5:inst19 ;
; |div5:inst20| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CH8_Matrix|div5:inst20 ;
; |div_mult:inst16| ; 9 (9) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CH8_Matrix|div_mult:inst16 ;
; |div_mult:inst23| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CH8_Matrix|div_mult:inst23 ;
; |div_mult:inst8| ; 9 (9) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CH8_Matrix|div_mult:inst8 ;
; |gating_pulse:inst| ; 91 (91) ; 40 (40) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CH8_Matrix|gating_pulse:inst ;
; |lpm_dff0:inst2| ; 1 (0) ; 14 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CH8_Matrix|lpm_dff0:inst2 ;
; |lpm_ff:lpm_ff_component| ; 1 (1) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CH8_Matrix|lpm_dff0:inst2|lpm_ff:lpm_ff_component ;
; |my_DFF:inst10| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CH8_Matrix|my_DFF:inst10 ;
; |my_DFF:inst13| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CH8_Matrix|my_DFF:inst13 ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+---------------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+---------------------------------------------+
; inst2/lpm_ff_component/dffs[13] ; Merged with inst2/lpm_ff_component/dffs[15] ;
; inst2/lpm_ff_component/dffs[14] ; Merged with inst2/lpm_ff_component/dffs[15] ;
; inst/TP ; Merged with inst/TB ;
; inst23/counter[2] ; Lost fanout ;
; inst23/counter[3] ; Lost fanout ;
; inst23/counter[4] ; Lost fanout ;
; inst23/counter[5] ; Lost fanout ;
; inst23/counter[6] ; Lost fanout ;
; inst23/counter[7] ; Lost fanout ;
; inst23/counter[8] ; Lost fanout ;
; Total Number of Removed Registers = 10 ; ;
+----------------------------------------+---------------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 84 ;
; Number of registers using Synchronous Clear ; 29 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 32 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------+
; 4:1 ; 19 bits ; 38 LEs ; 19 LEs ; 19 LEs ; Yes ; |CH8_Matrix|gating_pulse:inst|counter_big[0] ;
; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |CH8_Matrix|gating_pulse:inst|counter_small_SLWR[4] ;
; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |CH8_Matrix|gating_pulse:inst|counter_small_AD[4] ;
; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |CH8_Matrix|gating_pulse:inst|counter_small_Get[4] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------+
+-------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_dff0:inst2|lpm_ff:lpm_ff_component ;
+------------------------+------------+-----------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+------------+-----------------------------------------------+
; LPM_WIDTH ; 16 ; Signed Integer ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_FFTYPE ; DFF ; Untyped ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Wed Jun 04 13:11:57 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CH8_Matrix -c CH8_Matrix
Info: Found 1 design units, including 1 entities, in source file CH8_Matrix.bdf
Info: Found entity 1: CH8_Matrix
Info: Found 1 design units, including 1 entities, in source file my_DFF.v
Info: Found entity 1: my_DFF
Info: Found 1 design units, including 1 entities, in source file update_pulse.v
Info: Found entity 1: update_pulse
Info: Found 1 design units, including 1 entities, in source file lpm_dff0.v
Info: Found entity 1: lpm_dff0
Info: Found 1 design units, including 1 entities, in source file HM_address.v
Info: Found entity 1: HM_address
Info: Found 1 design units, including 1 entities, in source file HM_Tab.v
Info: Found entity 1: HM_Tab
Info: Found 1 design units, including 1 entities, in source file div5.v
Info: Found entity 1: div5
Info: Found 1 design units, including 1 entities, in source file DDS_straight.v
Info: Found entity 1: DDS_straight
Info: Found 1 design units, including 1 entities, in source file gating_pulse.v
Info: Found entity 1: gating_pulse
Info: Found 1 design units, including 1 entities, in source file bit_cut.v
Info: Found entity 1: bit_cut
Info: Found 1 design units, including 1 entities, in source file AD_2Compl.v
Info: Found entity 1: AD_2Compl
Info: Found 1 design units, including 1 entities, in source file div_mult.v
Info: Found entity 1: div_mult
Info: Found 1 design units, including 1 entities, in source file widen_bit.v
Info: Found entity 1: widen_bit
Info: Found 1 design units, including 1 entities, in source file DDS_straight_new.v
Info: Found entity 1: DDS_straight_new
Info: Found 1 design units, including 1 entities, in source file wait2s.v
Info: Found entity 1: wait2s
Info: Found 1 design units, including 1 entities, in source file counter.v
Info: Found entity 1: counter
Info: Elaborating entity "CH8_Matrix" for the top level hierarchy
Warning: Block or symbol "NOT" of instance "inst118" overlaps another block or symbol
Info: Elaborating entity "gating_pulse" for hierarchy "gating_pulse:inst"
Info: Elaborating entity "my_DFF" for hierarchy "my_DFF:inst13"
Info: Elaborating entity "div5" for hierarchy "div5:inst19"
Info: Elaborating entity "div_mult" for hierarchy "div_mult:inst23"
Info: Elaborating entity "lpm_dff0" for hierarchy "lpm_dff0:inst2"
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartusii/quartus/libraries/megafunctions/lpm_ff.tdf
Info: Found entity 1: lpm_ff
Info: Elaborating entity "lpm_ff" for hierarchy "lpm_dff0:inst2|lpm_ff:lpm_ff_component"
Info: Elaborated megafunction instantiation "lpm_dff0:inst2|lpm_ff:lpm_ff_component"
Info: Elaborating entity "widen_bit" for hierarchy "widen_bit:inst7"
Info: Elaborating entity "AD_2Compl" for hierarchy "AD_2Compl:inst3"
Info: Duplicate registers merged to single register
Info: Duplicate register "lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[13]" merged to single register "lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[15]"
Info: Duplicate register "lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[14]" merged to single register "lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[15]"
Info: Duplicate registers merged to single register
Info: Duplicate register "gating_pulse:inst|TP" merged to single register "gating_pulse:inst|TB"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "RDY0" stuck at VCC
Warning: Pin "PDWN8" stuck at GND
Info: 7 registers lost all their fanouts during netlist optimizations. The first 7 are displayed below.
Info: Register "inst23/counter[2]" lost all its fanouts during netlist optimizations.
Info: Register "inst23/counter[3]" lost all its fanouts during netlist optimizations.
Info: Register "inst23/counter[4]" lost all its fanouts during netlist optimizations.
Info: Register "inst23/counter[5]" lost all its fanouts during netlist optimizations.
Info: Register "inst23/counter[6]" lost all its fanouts during netlist optimizations.
Info: Register "inst23/counter[7]" lost all its fanouts during netlist optimizations.
Info: Register "inst23/counter[8]" lost all its fanouts during netlist optimizations.
Info: Implemented 188 device resources after synthesis - the final resource count might be different
Info: Implemented 17 input pins
Info: Implemented 29 output pins
Info: Implemented 142 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Allocated 128 megabytes of memory during processing
Info: Processing ended: Wed Jun 04 13:12:04 2008
Info: Elapsed time: 00:00:07
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.map.smsg.
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