div.tan.rpt

CPLD原始代码程序

+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[0] ; q~reg0   ; clk        ; clk      ; None                        ; None                      ; 2.433 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; q~reg0   ; q~reg0   ; clk        ; clk      ; None                        ; None                      ; 2.350 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[0] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 2.153 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; q~reg0   ; clk        ; clk      ; None                        ; None                      ; 2.145 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[2] ; q~reg0   ; clk        ; clk      ; None                        ; None                      ; 2.127 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[2] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 2.125 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[2] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 2.125 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[2] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 2.124 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[1] ; q~reg0   ; clk        ; clk      ; None                        ; None                      ; 2.100 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[1] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 2.069 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 2.054 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 2.052 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 2.049 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[0] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 1.824 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[0] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 1.822 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[0] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 1.813 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[1] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 1.605 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[1] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 1.603 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[1] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 1.592 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; count[3] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 1.583 ns                ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------+
; tco                                                          ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From   ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A   ; None         ; 6.854 ns   ; q~reg0 ; q  ; clk        ;
+-------+--------------+------------+--------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Apr 16 09:25:00 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div -c div
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 304.04 MHz between source register "count[0]" and destination register "q~reg0"
    Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.433 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y4_N5; Fanout = 5; REG Node = 'count[0]'
            Info: 2: + IC(1.026 ns) + CELL(0.511 ns) = 1.537 ns; Loc. = LC_X2_Y4_N3; Fanout = 1; COMB Node = 'count[0]~187'
            Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 2.433 ns; Loc. = LC_X2_Y4_N4; Fanout = 2; REG Node = 'q~reg0'
            Info: Total cell delay = 1.102 ns ( 45.29 % )
            Info: Total interconnect delay = 1.331 ns ( 54.71 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y4_N4; Fanout = 2; REG Node = 'q~reg0'
                Info: Total cell delay = 2.081 ns ( 62.16 % )
                Info: Total interconnect delay = 1.267 ns ( 37.84 % )
            Info: - Longest clock path from clock "clk" to source register is 3.348 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y4_N5; Fanout = 5; REG Node = 'count[0]'
                Info: Total cell delay = 2.081 ns ( 62.16 % )
                Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: + Micro clock to output delay of source is 0.376 ns
        Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "q" through register "q~reg0" is 6.854 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X2_Y4_N4; Fanout = 2; REG Node = 'q~reg0'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 3.130 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y4_N4; Fanout = 2; REG Node = 'q~reg0'
        Info: 2: + IC(0.808 ns) + CELL(2.322 ns) = 3.130 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'q'
        Info: Total cell delay = 2.322 ns ( 74.19 % )
        Info: Total interconnect delay = 0.808 ns ( 25.81 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Wed Apr 16 09:25:01 2008
    Info: Elapsed time: 00:00:01