tb_tx_rx.v

FPGA芯片与ADI公司的AD9779之间的通信

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:50:00 12/09/2008
// Design Name:   DDR_RX
// Module Name:   F:/LAB/LVDS/LVDS_S3/TB_TX_RX.v
// Project Name:  LVDS_S3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: DDR_RX
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TB_TX_RX;

	wire [7:0] DATA_P;
	wire [7:0] DATA_N;
	wire CTRL_P;
   wire CTRL_N;
	wire CLOCK_P;
	wire CLOCK_N;
	reg DAC_CLK_P;
	reg DAC_CLK_N;
	reg USER_CLK;
	reg RESET;


	// Instantiate the Unit Under Test (UUT)
	DDR_RX uut_rx (
		.DATA_RX_P(DATA_P), 
		.DATA_RX_N(DATA_N), 
		.CLOCK_RX_P(CLOCK_P), 
		.CLOCK_RX_N(CLOCK_N), 
		.DATA_RX_FIFO(DATA_RX_FIFO), 
		.DAC_CLK_P(DAC_CLK_P), 
		.DAC_CLK_N(DAC_CLK_N), 
		.RESET(RESET),
		.CTRL_RX_P(CTRL_P),
      .CTRL_RX_N(CTRL_N)
	);
	
	DDR_TX_TEST uut_tx(
		.DATA_TX_P(DATA_P),
      .DATA_TX_N(DATA_N),
      .CLOCK_TX_P(CLOCK_P),
      .CLOCK_TX_N(CLOCK_N),
		.USER_CLK(USER_CLK),
		.RESET(RESET),
		.CTRL_TX_P(CTRL_P),
      .CTRL_TX_N(CTRL_N)
    );

	initial begin
	   USER_CLK = 0;
		forever #(4) USER_CLK = ~USER_CLK;
	end
	
	initial begin
	   DAC_CLK_P = 0;
		DAC_CLK_N = 1;
		forever #(2) 
		begin
			DAC_CLK_P = ~DAC_CLK_P;
			DAC_CLK_N = ~DAC_CLK_N;
		end
	end

	initial begin

		RESET = 1;
		//DATA_TX_VLD =0;	
		//DATA_TX_FIFO = 32'h1000_0000;

		// Wait 10 ns for global reset to finish
		#10;
		RESET = 0;
		//#200;
		//DATA_TX_VLD =1;		
		//forever #(8) DATA_TX_FIFO = DATA_TX_FIFO + 32'h0001_0001;
		
	end
      
endmodule