ddr_tx_test_map.mrp
来自「FPGA芯片与ADI公司的AD9779之间的通信」· MRP 代码 · 共 480 行 · 第 1/3 页
MRP
480 行
| DATA_TX_N_2<14> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<15> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<0> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<1> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<2> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<3> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<4> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<5> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<6> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<7> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<8> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<9> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<10> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<11> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<12> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<13> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<14> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_3<15> | IOBS | OUTPUT | See master | | | | | || DATA_TX_P_0<0> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<1> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<2> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<3> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<4> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<5> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<6> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<7> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<8> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<9> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<10> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<11> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<12> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<13> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<14> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_0<15> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<0> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<1> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<2> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<3> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<4> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<5> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<6> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<7> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<8> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<9> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<10> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<11> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<12> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<13> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<14> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_1<15> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<0> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<1> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<2> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<3> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<4> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<5> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<6> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<7> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<8> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<9> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<10> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<11> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<12> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<13> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<14> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_2<15> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<0> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<1> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<2> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<3> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<4> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<5> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<6> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<7> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<8> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<9> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<10> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<11> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<12> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<13> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<14> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_P_3<15> | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || RESET_N | IOB | INPUT | LVCMOS25 | | | | | || RESET_SYS_N | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || USER_CLK | IOB | INPUT | LVCMOS25 | | | | | || dbg_clk_30 | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dbg_clk_122 | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |+----------------------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status------------------------------- No Partitions were found in this design.-------------------------------Area Group Information---------------------- No area groups were found in this design.----------------------Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Development System Reference Guide "TRACE" chapter.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Control Set Information------------------------------------Use the "-detail" map option to print out Control Set Information.Section 14 - Utilization by Hierarchy-------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48E | BUFG | BUFIO | BUFR | DCM | PLL | Full Hierarchical Name |+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+| DDR_TX_TEST/ | | 35/44 | 128/147 | 136/140 | 0/0 | 0/0 | 0/0 | 1/2 | 0/0 | 0/0 | 0/0 | 0/1 | DDR_TX_TEST || +u_DDR_TX_TOP | | 9/9 | 19/19 | 4/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | DDR_TX_TEST/u_DDR_TX_TOP || ++u_DDR_TX_0 | | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | DDR_TX_TEST/u_DDR_TX_TOP/u_DDR_TX_0 || ++u_DDR_TX_1 | | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | DDR_TX_TEST/u_DDR_TX_TOP/u_DDR_TX_1 || ++u_DDR_TX_2 | | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | DDR_TX_TEST/u_DDR_TX_TOP/u_DDR_TX_2 || ++u_DDR_TX_3 | | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | DDR_TX_TEST/u_DDR_TX_TOP/u_DDR_TX_3 || +u_PLL_tx | | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 1/1 | DDR_TX_TEST/u_PLL_tx |+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+* Slices can be packed with basic elements from multiple hierarchies. Therefore, a slice will be counted in every hierarchical module that each of its packed basic elements belong to.** For each column, there are two numbers reported <A>/<B>. <A> is the number of elements that belong to that specific hierarchical module. <B> is the total number of elements from that hierarchical module and any lower level hierarchical modules below.*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.⌨️ 快捷键说明
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