📄 ddr_tx_test_map.mrp
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unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[3].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[4].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[5].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[6].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[7].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[8].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[9].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[10].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[11].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[12].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[13].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[14].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[15].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/u_ODDR_clk has an unexpected
'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[0].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[1].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[2].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[3].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[4].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[5].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[6].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[7].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[8].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[9].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[10].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[11].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[12].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[13].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[14].u_ODDR_data has an
unexpected 'INITSTATE' property.WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_3/um_O[15].u_ODDR_data has an
unexpected 'INITSTATE' property.Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:856 - PLL_ADV u_PLL_tx/PLL_ADV_INST CLKIN2 pin was disconnected
because a constant 1 is driving the CLKINSEL pin.INFO:MapLib:841 - Changing COMPENSATION attribute from SYSTEM_SYNCHRONOUS to
INTERNAL for PLL_ADV u_PLL_tx/PLL_ADV_INST.INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to
1.050 Volts)INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).INFO:Place:834 - Only a subset of IOs are locked. Out of 142 IOs, 141 are locked
and 1 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. INFO:Pack:1650 - Map created a placed design.Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+----------------------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+----------------------------------------------------------------------------------------------------------------------------------------+| CLK_50M | IOB | INPUT | LVCMOS25 | | | | | || CLOCK_TX_N_0 | IOBS | OUTPUT | See master | | | | | || CLOCK_TX_N_1 | IOBS | OUTPUT | See master | | | | | || CLOCK_TX_N_2 | IOBS | OUTPUT | See master | | | | | || CLOCK_TX_N_3 | IOBS | OUTPUT | See master | | | | | || CLOCK_TX_P_0 | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || CLOCK_TX_P_1 | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || CLOCK_TX_P_2 | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || CLOCK_TX_P_3 | IOBM | OUTPUT | LVDSEXT_25 | | | ODDR | | || DATA_TX_N_0<0> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<1> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<2> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<3> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<4> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<5> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<6> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<7> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<8> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<9> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<10> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<11> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<12> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<13> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<14> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_0<15> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<0> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<1> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<2> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<3> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<4> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<5> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<6> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<7> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<8> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<9> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<10> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<11> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<12> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<13> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<14> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_1<15> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<0> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<1> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<2> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<3> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<4> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<5> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<6> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<7> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<8> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<9> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<10> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<11> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<12> | IOBS | OUTPUT | See master | | | | | || DATA_TX_N_2<13> | IOBS | OUTPUT | See master | | | | | |⌨️ 快捷键说明
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