ddr_tx_test_map.mrp

FPGA芯片与ADI公司的AD9779之间的通信

Release 10.1.02 Map K.37 (nt)
Xilinx Mapping Report File for Design 'DDR_TX_TEST'

Design Information
------------------
Command Line   : map -ise
E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise
-intstyle ise -p xc5vfx130t-ff1738-1 -w -logic_opt off -ol high -t 1 -cm area
-pr off -k 6 -lc off -power off -o DDR_TX_TEST_map.ncd DDR_TX_TEST.ngd
DDR_TX_TEST.pcf 
Target Device  : xc5vfx130t
Target Package : ff1738
Target Speed   : -1
Mapper Version : virtex5 -- $Revision: 1.46.12.2 $
Mapped Date    : Tue Feb 17 17:35:06 2009

Design Summary
--------------
Number of errors:      0
Number of warnings:   69
Slice Logic Utilization:
  Number of Slice Registers:                   147 out of  81,920    1%
    Number used as Flip Flops:                 147
  Number of Slice LUTs:                        140 out of  81,920    1%
    Number used as logic:                      131 out of  81,920    1%
      Number using O6 output only:               3
      Number using O5 output only:             119
      Number using O5 and O6:                    9
    Number used as exclusive route-thru:         9
  Number of route-thrus:                       128 out of 163,840    1%
    Number using O6 output only:               128

Slice Logic Distribution:
  Number of occupied Slices:                    41 out of  20,480    1%
  Number of LUT Flip Flop pairs used:          150
    Number with an unused Flip Flop:             3 out of     150    2%
    Number with an unused LUT:                  10 out of     150    6%
    Number of fully used LUT-FF pairs:         137 out of     150   91%
    Number of unique control sets:               4
    Number of slice register sites lost
      to control set restrictions:               9 out of  81,920    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       142 out of     840   16%
    IOB Flip Flops:                             68
    IOB Master Pads:                            68
    IOB Slave Pads:                             68

Specific Feature Utilization:
  Number of BUFG/BUFGCTRLs:                      2 out of      32    6%
    Number used as BUFGs:                        2
  Number of PLL_ADVs:                            1 out of       6   16%

Peak Memory Usage:  496 MB
Total REAL time to MAP completion:  2 mins 48 secs 
Total CPU time to MAP completion:   1 mins 34 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/u_ODDR_clk has an unexpected
   'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[0].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[1].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[2].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[3].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[4].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[5].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[6].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[7].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[8].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[9].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[10].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[11].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[12].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[13].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[14].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_0/um_O[15].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/u_ODDR_clk has an unexpected
   'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[0].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[1].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[2].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[3].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[4].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[5].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[6].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[7].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[8].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[9].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[10].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[11].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[12].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[13].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[14].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_1/um_O[15].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/u_ODDR_clk has an unexpected
   'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[0].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[1].u_ODDR_data has an
   unexpected 'INITSTATE' property.
WARNING:Pack:614 - Symbol u_DDR_TX_TOP/u_DDR_TX_2/um_O[2].u_ODDR_data has an